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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
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hitachi superh risc engine SH7018 hardware manual ade-602-186 rev. 1.0 3/4/03 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products.
preface the SH7018 is a single-chip risc (reduced instruction set computer) microcomputer with a cpu based on hitachi-original risc-type superh* architecture as its core. it also provides peripheral functions essential to system composition. the cpu incorporated into the chip supports the risc instruction set. basic instructions execute in one cycle (one system clock cycle), so instruction execution times are extremely fast. the chip has an internal 32-bit architecture for efficient data processing. the cpu is capable of supporting applications employing real-time control. such applications were not practical using previous microcomputers due to the extremely fast processing speeds required. it makes possible the development of systems providing high performance and excellent functionality at low cost. the chip incorporates several peripheral functions essential to system composition, such as rom, ram, timers, serial communication interface (sci), a/d converter, interrupt controller (intc), and i/o ports. it also supports external memory access, which allows for efficient connections to external memory and lsi devices. these features help to reduce system costs substantially. the SH7018 employs on-chip flash memory with f-ztat* (flexible zero turnaround time). in addition to allowing programming of the chip by writing to it using a program writer for lsi devices, software can be written to the flash memory and erased as necessary. this hardware manual describes the hardware features of the SH7018. for detailed information on the supported instructions, please refer to the programming manual. note: * superh and f-ztat are trademarks of hitachi, ltd. related manuals sh-1/sh-2/sh-dsp programming manual. for information on development environment systems, please contact a hitachi sales office.

i contents section 1 SH7018 overview ............................................................................................ 1 1.1 SH7018 features............................................................................................................. ... 1 1.2 block diagram............................................................................................................... .... 5 1.3 pin description ............................................................................................................. ..... 6 1.3.1 pin layout ............................................................................................................ 6 1.3.2 pin functions........................................................................................................ 7 section 2 cpu ....................................................................................................................... 11 2.1 register configuration ...................................................................................................... 11 2.1.1 general registers (rn) ......................................................................................... 11 2.1.2 control registers.................................................................................................. 12 2.1.3 system registers .................................................................................................. 13 2.1.4 initial values of registers ................................................................................... 13 2.2 data formats................................................................................................................ ...... 14 2.2.1 data format in registers...................................................................................... 14 2.2.2 data format in memory ....................................................................................... 14 2.2.3 immediate data format........................................................................................ 14 2.3 instruction features ........................................................................................................ ... 15 2.3.1 risc-type instruction set ................................................................................... 15 2.3.2 addressing modes................................................................................................ 18 2.3.3 instruction format ................................................................................................ 22 2.4 instruction set by classification........................................................................................ 25 2.5 processing states ........................................................................................................... .... 38 2.5.1 state transitions ................................................................................................... 38 2.5.2 power-down state................................................................................................ 39 section 3 operating modes ............................................................................................... 41 3.1 operating mode selection ................................................................................................. 41 3.2 description of operating modes ....................................................................................... 41 3.3 pin configuration ........................................................................................................... ... 42 section 4 clock pulse generator (cpg) ....................................................................... 43 4.1 overview.................................................................................................................... ........ 43 4.2 clock source................................................................................................................ ...... 43 4.2.1 crystal resonator connection.............................................................................. 43 4.2.2 external clock input ............................................................................................ 45 4.3 usage notes ................................................................................................................. ...... 45
ii section 5 exception processing ....................................................................................... 47 5.1 overview.................................................................................................................... ........ 47 5.1.1 types of exception processing and priority ........................................................ 47 5.1.2 exception processing operations ......................................................................... 48 5.1.3 exception processing vector table...................................................................... 49 5.2 resets...................................................................................................................... ........... 51 5.2.1 reset ..................................................................................................................... 51 5.2.2 power-on reset.................................................................................................... 51 5.3 address errors .............................................................................................................. ..... 52 5.3.1 address error exception processing.................................................................... 52 5.4 interrupts.................................................................................................................. .......... 53 5.4.1 interrupt priority level......................................................................................... 53 5.4.2 interrupt exception processing ............................................................................ 54 5.5 exceptions triggered by instructions................................................................................ 54 5.5.1 trap instructions .................................................................................................. 55 5.5.2 illegal slot instructions ........................................................................................ 55 5.5.3 general illegal instructions .................................................................................. 55 5.6 when exception sources are not accepted..................................................................... 56 5.6.1 immediately after a delayed branch instruction.................................................. 56 5.6.2 immediately after an interrupt-disabled instruction............................................ 56 5.7 stack status after exception processing ends................................................................... 57 5.8 notes on use................................................................................................................ ...... 58 5.8.1 value of stack pointer (sp).................................................................................. 58 5.8.2 value of vector base register (vbr) ................................................................. 58 5.8.3 address errors caused by stacking of address error exception processing...... 58 section 6 interrupt controller (intc) ........................................................................... 59 6.1 overview.................................................................................................................... ........ 59 6.1.1 features ................................................................................................................ 59 6.1.2 block diagram...................................................................................................... 60 6.1.3 pin configuration ................................................................................................. 61 6.1.4 register configuration ......................................................................................... 61 6.2 interrupt sources........................................................................................................... ..... 62 6.2.1 nmi interrupts...................................................................................................... 62 6.2.2 irq interrupts ...................................................................................................... 62 6.2.3 on-chip peripheral module interrupts ................................................................ 63 6.2.4 interrupt exception vectors and priority rankings ............................................. 63 6.3 description of registers .................................................................................................... 66 6.3.1 interrupt priority registers a to h (ipra to iprh) ............................................ 66 6.3.2 interrupt control register (icr) .......................................................................... 67 6.3.3 irq status register (isr) .................................................................................... 68 6.4 interrupt operation ......................................................................................................... ... 70
iii 6.4.1 interrupt sequence................................................................................................ 70 6.4.2 stack after interrupt exception processing .......................................................... 72 6.5 interrupt response time.................................................................................................... 7 2 section 7 bus state controller (bsc) ............................................................................ 75 7.1 overview.................................................................................................................... ........ 75 7.1.1 features ................................................................................................................ 75 7.1.2 block diagram...................................................................................................... 76 7.1.3 pin configuration ................................................................................................. 77 7.1.4 register configuration ......................................................................................... 77 7.1.5 address map ........................................................................................................ 78 7.2 description of registers .................................................................................................... 80 7.2.1 bus control register 1 (bcr1)............................................................................ 80 7.2.2 bus control register 2 (bcr2)............................................................................ 82 7.2.3 wait control register 1 (wcr1) ......................................................................... 86 7.3 accessing ordinary space................................................................................................. 88 7.3.1 basic timing ........................................................................................................ 88 7.3.2 wait state control ................................................................................................ 89 7.3.3 cs assert period extension.................................................................................. 91 7.4 waits between access cycles ........................................................................................... 92 7.4.1 prevention of data bus conflicts ......................................................................... 92 7.4.2 simplification of bus cycle start detection ........................................................ 93 7.5 memory connection examples ......................................................................................... 94 section 8 multifunction timer pulse unit (mtu) .................................................... 95 8.1 overview.................................................................................................................... ........ 95 8.1.1 features ................................................................................................................ 95 8.1.2 block diagram...................................................................................................... 98 8.1.3 pin configuration ................................................................................................. 99 8.1.4 register configuration ......................................................................................... 100 8.2 mtu register descriptions............................................................................................... 101 8.2.1 timer control register (tcr) ............................................................................. 101 8.2.2 timer mode register (tmdr) ............................................................................ 105 8.2.3 timer i/o control register (tior) ..................................................................... 106 8.2.4 timer interrupt enable register (tier) .............................................................. 114 8.2.5 timer status register (tsr) ................................................................................ 116 8.2.6 timer counters (tcnt)....................................................................................... 118 8.2.7 timer general register (tgr) ............................................................................ 119 8.2.8 timer start register (tstr)................................................................................ 119 8.2.9 timer synchro register (tsyr).......................................................................... 120 8.3 bus master interface........................................................................................................ .. 121 8.3.1 16-bit registers.................................................................................................... 121 8.3.2 8-bit registers...................................................................................................... 121
iv 8.4 operation ................................................................................................................... ........ 123 8.4.1 overview .............................................................................................................. 123 8.4.2 basic functions .................................................................................................... 123 8.4.3 synchronous operation ........................................................................................ 129 8.4.4 buffer operation .................................................................................................. 131 8.4.5 cascade connection mode ................................................................................... 134 8.4.6 pwm mode .......................................................................................................... 135 8.5 interrupts.................................................................................................................. .......... 140 8.5.1 interrupt sources and priority ranking................................................................ 140 8.5.2 a/d converter activation .................................................................................... 141 8.6 operation timing ............................................................................................................ .. 142 8.6.1 input/output timing ............................................................................................ 142 8.6.2 interrupt signal timing ........................................................................................ 146 8.7 notes and precautions....................................................................................................... . 148 8.8 mtu output pin initialization .......................................................................................... 157 8.8.1 operating modes .................................................................................................. 157 8.8.2 reset start operation............................................................................................ 158 8.8.3 operation in case of re-setting due to error during operation, etc................. 158 8.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. ......................................................................................... 159 section 9 8-bit timer 2 (tim2) ...................................................................................... 169 9.1 overview.................................................................................................................... ........ 169 9.1.1 features ................................................................................................................ 16 9 9.1.2 block diagram...................................................................................................... 170 9.1.3 register configuration ......................................................................................... 170 9.2 register descriptions....................................................................................................... .. 171 9.2.1 timer 2 control/status register (t2csr) ........................................................... 171 9.2.2 timer 2 counter (t2cnt) ................................................................................... 172 9.2.3 timer 2 constant register (t2cor) ................................................................... 173 9.3 operation ................................................................................................................... ........ 174 9.3.1 cyclic count operation........................................................................................ 174 9.3.2 t2cnt count timing.......................................................................................... 174 9.4 interrupts.................................................................................................................. .......... 175 9.4.1 interrupt source.................................................................................................... 175 9.4.2 timing of compare match flag setting .............................................................. 175 9.4.3 timing of compare match flag clearing ............................................................ 176 section 10 compare match timer (cmt) ................................................................... 177 10.1 overview................................................................................................................... ......... 177 10.1.1 features ................................................................................................................ 1 77 10.1.2 block diagram...................................................................................................... 178 10.1.3 register configuration ......................................................................................... 179
v 10.2 register descriptions...................................................................................................... ... 180 10.2.1 compare match timer start register (cmstr) ................................................. 180 10.2.2 compare match timer control/status register (cmcsr).................................. 181 10.2.3 compare match timer counter (cmcnt).......................................................... 182 10.2.4 compare match timer constant register (cmcor).......................................... 183 10.3 operation .................................................................................................................. ......... 183 10.3.1 period count operation........................................................................................ 183 10.3.2 cmcnt count timing ........................................................................................ 184 10.4 interrupts................................................................................................................. ........... 184 10.4.1 interrupt sources .................................................................................................. 184 10.4.2 compare match flag set timing ......................................................................... 184 10.4.3 compare match flag clear timing...................................................................... 185 10.5 notes on use............................................................................................................... ....... 186 10.5.1 contention between cmcnt write and compare match ................................... 186 10.5.2 contention between cmcnt word write and incrementation .......................... 187 10.5.3 contention between cmcnt byte write and incrementation ............................ 188 section 11 watchdog timer (wdt) .............................................................................. 189 11.1 overview................................................................................................................... ......... 189 11.1.1 features ................................................................................................................ 1 89 11.1.2 block diagram...................................................................................................... 190 11.1.3 register configuration ......................................................................................... 191 11.2 register descriptions...................................................................................................... ... 191 11.2.1 timer counter (tcnt) ........................................................................................ 191 11.2.2 timer control/status register (tcsr) ................................................................ 192 11.2.3 reset control/status register (rstcsr) ............................................................ 193 11.2.4 register access .................................................................................................... 194 11.3 operation .................................................................................................................. ......... 195 11.3.1 watchdog timer mode ........................................................................................ 195 11.3.2 interval timer mode ............................................................................................ 197 11.3.3 clearing the standby mode.................................................................................. 197 11.3.4 timing of setting the overflow flag (ovf)........................................................ 198 11.3.5 timing of setting the watchdog timer overflow flag (wovf)........................ 198 11.4 notes on use............................................................................................................... ....... 199 11.4.1 tcnt write and increment contention............................................................... 199 11.4.2 changing cks2 to cks0 bit values................................................................... 199 11.4.3 changing between watchdog timer/interval timer modes................................ 199 11.4.4 internal reset with the watchdog timer ............................................................ 199 section 12 serial communication interface (sci1) .................................................. 201 12.1 overview................................................................................................................... ......... 201 12.1.1 features ................................................................................................................ 2 01 12.1.2 block diagram...................................................................................................... 202
vi 12.1.3 pin configuration ................................................................................................. 202 12.1.4 register configuration ......................................................................................... 203 12.2 register descriptions...................................................................................................... ... 203 12.2.1 receive shift register (rsr1)............................................................................. 203 12.2.2 receive data register (rdr1) ............................................................................ 203 12.2.3 transmit shift register (tsr1)............................................................................ 204 12.2.4 transmit data register (tdr1) .......................................................................... 204 12.2.5 serial mode register (smr1).............................................................................. 204 12.2.6 serial control register (scr1)............................................................................ 207 12.2.7 serial status register (ssr1)............................................................................... 210 12.2.8 bit rate register (brr1)..................................................................................... 214 12.3 operation .................................................................................................................. ......... 225 12.3.1 overview .............................................................................................................. 225 12.3.2 operation in asynchronous mode........................................................................ 227 12.3.3 multiprocessor communication ........................................................................... 237 12.3.4 clock synchronous operation.............................................................................. 245 12.4 interrupt .................................................................................................................. ........... 255 12.5 notes on use............................................................................................................... ....... 256 section 13 a/d converter (a/d) ..................................................................................... 259 13.1 overview................................................................................................................... ......... 259 13.1.1 features ................................................................................................................ 2 59 13.1.2 block diagram...................................................................................................... 260 13.1.3 pin configuration ................................................................................................. 261 13.1.4 register configuration ......................................................................................... 262 13.2 register descriptions...................................................................................................... ... 262 13.2.1 a/d data registers a to d (addra to addrd).............................................. 262 13.2.2 a/d control/status register (adcsr)................................................................ 263 13.2.3 a/d control register (adcr)............................................................................. 265 13.3 cpu interface .............................................................................................................. ...... 266 13.4 operation .................................................................................................................. ......... 268 13.4.1 single mode (scan = 0) ..................................................................................... 268 13.4.2 scan mode (scan = 1) ....................................................................................... 270 13.4.3 input sampling and a/d conversion time.......................................................... 272 13.4.4 mtu trigger input timing.................................................................................. 274 13.5 a/d conversion precision definitions.............................................................................. 274 13.6 notes on use............................................................................................................... ....... 276 13.6.1 analog voltage settings....................................................................................... 276 13.6.2 handling of analog input pins............................................................................. 276 section 14 pin function controller (pfc) .................................................................... 279 14.1 overview................................................................................................................... ......... 279 14.2 register configuration ..................................................................................................... . 282
vii 14.3 register descriptions...................................................................................................... ... 283 14.3.1 port a io register l (paiorl) .......................................................................... 283 14.3.2 port a control registers l1 and l2 (pacrl1, pacrl2) ................................. 283 14.3.3 port b io register (pbior)................................................................................. 288 14.3.4 port b control registers 1 and 2 (pvcr1, pbcr2)............................................ 288 14.3.5 port c io register (pcior)................................................................................. 291 14.3.6 port c control register (pccr) .......................................................................... 292 14.3.7 port d io register l (pdiorl) .......................................................................... 295 14.3.8 port d control register l (pdcrl).................................................................... 296 14.3.9 port e io register (peior) ................................................................................. 298 14.3.10 port e control register 2 (pecr2)...................................................................... 299 section 15 i/o ports (i/o) .................................................................................................. 301 15.1 overview................................................................................................................... ......... 301 15.2 port a..................................................................................................................... ............ 301 15.2.1 register configuration ......................................................................................... 302 15.2.2 port a data register l (padrl) ........................................................................ 303 15.3 port b ..................................................................................................................... ............ 304 15.3.1 register configuration ......................................................................................... 304 15.3.2 port b data register (pbdr)............................................................................... 305 15.4 port c ..................................................................................................................... ............ 306 15.4.1 register configuration ......................................................................................... 306 15.4.2 port c data register (pcdr)............................................................................... 307 15.5 port d..................................................................................................................... ............ 308 15.5.1 register configuration ......................................................................................... 308 15.5.2 port d data register l (pddrl) ........................................................................ 309 15.6 port e ..................................................................................................................... ............ 310 15.6.1 register configuration ......................................................................................... 310 15.6.2 port e data register (pedr) ............................................................................... 311 15.7 port f ..................................................................................................................... ............ 312 15.7.1 register configuration ......................................................................................... 312 15.7.2 port e data register (pfdr) ............................................................................... 313 section 16 160 kb flash memory (f-ztat) .............................................................. 315 16.1 features................................................................................................................... ........... 315 16.2 overview................................................................................................................... ......... 316 16.2.1 block diagram...................................................................................................... 316 16.2.2 mode transitions.................................................................................................. 317 16.2.3 on-board programming modes ........................................................................... 318 16.2.4 flash memory emulation in ram....................................................................... 320 16.2.5 differences between boot mode and user program mode ................................. 321 16.2.6 block configuration ............................................................................................. 322 16.3 pin configuration .......................................................................................................... .... 322
viii 16.4 register configuration ..................................................................................................... . 323 16.5 register descriptions...................................................................................................... ... 324 16.5.1 flash memory control register 1 (flmcr1)..................................................... 324 16.5.2 flash memory control register 2 (flmcr2)..................................................... 327 16.5.3 erase block register 1 (ebr1)............................................................................ 328 16.5.4 erase block register 2 (ebr2)............................................................................ 328 16.5.5 ram emulation register (ramer) ................................................................... 329 16.6 on-board programming modes ........................................................................................ 330 16.6.1 boot mode............................................................................................................ 331 16.6.2 user program mode ............................................................................................. 335 16.7 programming/erasing flash memory................................................................................ 336 16.7.1 program mode...................................................................................................... 336 16.7.2 program-verify mode .......................................................................................... 337 16.7.3 erase mode........................................................................................................... 345 16.7.4 erase-verify mode ............................................................................................... 346 16.7.5 wait time widths in programming/erasing........................................................ 352 16.8 protection................................................................................................................. .......... 353 16.8.1 hardware protection............................................................................................. 353 16.8.2 software protection .............................................................................................. 354 16.8.3 error protection .................................................................................................... 355 16.9 flash memory emulation in ram.................................................................................... 357 16.10 note on flash memory programming/erasing .................................................................. 359 16.11 flash memory programmer mode ..................................................................................... 359 16.11.1 socket adapter pin correspondence diagram ..................................................... 360 16.11.2 programmer mode operation............................................................................... 362 16.11.3 memory read mode............................................................................................. 363 16.11.4 auto-program mode ............................................................................................ 366 16.11.5 auto-erase mode.................................................................................................. 368 16.11.6 status read mode................................................................................................. 370 16.11.7 status polling........................................................................................................ 37 1 16.11.8 programmer mode transition time..................................................................... 371 16.11.9 notes on memory programming ......................................................................... 372 section 17 ram ................................................................................................................... 373 17.1 overview................................................................................................................... ......... 373 section 18 power-down state .......................................................................................... 375 18.1 overview................................................................................................................... ......... 375 18.1.1 power-down states .............................................................................................. 375 18.1.2 related register.................................................................................................... 376 18.2 standby control register (sbycr).................................................................................. 377 18.3 sleep mode................................................................................................................. ....... 377 18.3.1 transition to sleep mode ..................................................................................... 377
ix 18.3.2 canceling sleep mode.......................................................................................... 378 18.4 standby mode............................................................................................................... ..... 378 18.4.1 transition to standby mode ................................................................................. 378 18.4.2 canceling the standby mode................................................................................ 380 18.4.3 standby mode application example.................................................................... 381 section 19 electrical characteristics .............................................................................. 383 19.1 absolute maximum ratings.............................................................................................. 383 19.2 dc characteristics ......................................................................................................... .... 384 19.3 ac characteristics ......................................................................................................... .... 387 19.3.1 clock timing........................................................................................................ 387 19.3.2 control signal timing.......................................................................................... 389 19.3.3 bus timing ........................................................................................................... 391 19.3.4 multifunction timer pulse unit timing .............................................................. 396 19.3.5 i/o port timing .................................................................................................... 397 19.3.6 serial communication interface timing.............................................................. 398 19.3.7 a/d converter timing ......................................................................................... 399 19.3.8 test conditions for ac characteristics................................................................ 401 19.4 a/d converter characteristics .......................................................................................... 402 appendix a on-chip peripheral module registers .................................................. 405 appendix b pin states ........................................................................................................ 410 b.1 pin states .................................................................................................................. ......... 410 b.2 bus-related signals and pin states ................................................................................... 411 appendix c product lineup ............................................................................................. 412 appendix d package dimensions ................................................................................... 413
x
1 section 1 SH7018 overview 1.1 SH7018 features the SH7018 is a cmos single-chip microcomputer with a cpu based on hitachi-original risc- type superh* architecture as its core. it also provides peripheral functions essential to system configuration. the cpu incorporated into the chip supports the risc (reduced instruction set computer) instruction set. basic instructions execute in one cycle, so instruction execution times are extremely fast. the chip has an internal 32-bit architecture for efficient data processing. the cpu is capable of supporting applications employing real-time control. such applications were not practical using previous microcomputers due to the extremely fast processing speeds required. it makes possible the development of systems providing high performance and excellent functionality at low cost. the chip incorporates several peripheral functions essential to system configuration, such as rom, ram, timers, serial communication interface (sci), a/d converter, interrupt controller (intc), and i/o ports. it also supports external memory access, which allows for efficient connections to external memory and lsi devices. these features help to reduce system costs substantially. the SH7018 employs on-chip flash memory with f-ztat* (flexible zero turnaround time). in addition to allowing programming of the chip by writing to it using a program writer for lsi devices, software can be written to the flash memory and erased as necessary. this allows the firmware to be overwritten at the user site while the chip is mounted on the circuit board. note: * superh and f-ztat are trademarks of hitachi, ltd.
2 table 1.1 features item specification cpu ? original hitachi architecture ? internal 32-bit configuration ? general register machine ? general registers: 32-bit 16 ? control registers: 32-bit 3 ? system registers: 32-bit 4 ? risc (reduced instruction set computer) instruction set ? instruction length: 16-bit fixed for efficient coding ? load-store architecture (basic operations executed between registers) ? extended branching instructions to minimize pipeline disturbance when branching ? instruction set based on c language ? instruction execution time of one cycle per instruction (50 ns per instruction when operating at 20 mhz) ? maximum address space of 4 gb supported by architecture ? on-chip multiplier the on-chip multiplier handles 32 32 64 multiplication operations in two to four cycles and 32 32 + 64 64 multiplication/accumulation operations in two to four cycles. ? pipeline 5-stage pipeline interrupt controller (intc) ? seven external interrupt pins (nmi, irq0 to irq3 , irq6 , irq7 ) ? 16-level priority setting supported bus state controller (bsc) ? bus access to external memory and external devices supported ? 8-bit fixed external data bus ? address space divided into four areas (sram space 4 areas) wait cycles may be specified (0 to 3 cycles) separately for each area. ? chip select signals corresponding to memory areas are output. ? wait cycles may be inserted using external wait signal.
3 table 1.1 features (cont) item specification multifunction timer pulse unit (mtu) 3 channels ? 16-bit free running counter 3 channels ? eight compare match registers ? interrupt requests are generated by compare match and overflow operations. compare match timer (cmt) 2 channels ? 16-bit free running counter 2 channels ? compare registers: 1 per channel ? interrupt requests are generated by compare match operations. watchdog timer (wdt) ? can be switched between watchdog timer and interval timer functions. ? internal reset or interrupt generated by counter overflow. 5 v i/o pins ? by specifying the power supply for the input/output circuitry, pv cc , the input/output voltage level for the following pins can be set to either 3.3 v or 5 v: res , nmi, irq0 , wait , d0 to d7, sck, txd, rxd, tioc0a, tioc0c (total 17 pins). 8-bit timer (tim2) ? 8-bit interval timer function ? interrupt generated by compare match operations. serial communication interface (sci) ? asynchronous or clock-synchronous mode is selectable (full duplex) ? on-chip dedicated baud rate generator ? multi-processor communication function i/o ports ? 62 inputs and outputs ? 8 inputs a/d converter ? 10 bits 8 channels ? built-in sample and hold function on-chip memory ? ram: 4 kb ? rom: 160 kb (f-ztat)
4 table 1.1 features (cont) item specification operating modes ? processing modes ? program execution mode ? exception processing mode ? operating modes ? extended rom enabled mode ? boot mode ? user program mode ? program mode ? low-power-consumption modes ? sleep mode ? standby mode clock pulse generator (cpg) on-chip clock pulse generator (1 : 1 oscillation using duty correction circuit) product lineup product name voltage operating frequency product code package SH7018 3.3 v 20 mhz hd64f7018x20 tfp-100b
5 1.2 block diagram pa15/ck pa14/rd pa12/wrl pa11/cs1 pa10/cs0 pa9/irq3 pa8/irq2 pa7/cs3 pa6/cs2 pa5/sck pa4/txd pa3/rxd pa2/irq0 pa1 pa0 pb9/irq7/a21 pb8/irq6/a20/wait pb7/a19 pb6/a18 pb5 pb4 pb3/irq1 pb2 pb1/a17 pb0/a16 pc15/a15 pc14/a14 pc13/a13 pc12/a12 pc11/a11 pc10/a10 pc9/a9 pc8/a8 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 port c port d pd7/d7 pd6/d6 pd5/d5 pd4/d4 pd3/d3 pd2/d2 pd1/d1 pd0/d0 pe14 pe13 pe12 pe11 pe10 pe9 pe8 pe7/tioc2b pe6/tioc2a pe5/tioc1b pe4/tioc1a pe2/tioc0c pe0/tioc0a pf7/an7 pf6/an6 pf5/an5 pf4/an4 pf3/an3 pf2/an2 pf1/an1 pf0/an0 : peripheral address bus : peripheral data bus : on-chip address bus : on-chip upper data : on-chip lower data nmi res md0 (vss) md1 (vcc) md2 (vss) md3 (vss) extal xtal fwp * vcc vcc vcc vcc vcc vcc vcc vcc pvcc avcc vss vss vss vss vss vss vss vss vss vss avss serial communication interface ( 1 channel) interrupt controller timers bus state controller a/d converter watch- dog timer cpu ram 4kb flash rom 160 kb multifunction timer pulse unit compare match 8-bit timer 3 2 1 port e port f note: * fwe during write mode port b port a figure 1.1 block diagram of SH7018 (tfp-100b pins)
6 1.3 pin description 1.3.1 pin layout vss pe4/tioc1a pe5/tioc1b vcc pe6/tioc2a pe7/tioc2b pe8 pe9 pe10 pe11 pe12 pe13 pe14 vss pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 avss pf6/an6 pf7/an7 avcc vcc top view (tfp-100b) vss pc0/a0 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 vss pc6/a6 pc7/a7 pc8/a8 pc9/a9 pc10/a10 pc11/a11 vcc pc12/a12 pc13/a13 pc14/a14 pc15/a15 pb0/a16 pb1/a17 vss pb2 pb3/irq1 vss pa15/ck vcc vcc md0 md1 fwp * md2 extal md3 xtal vss pe2/tioc0c pe0/tioc0a pd0/d0 pd1/d1 pd2/d2 pd3/d3 pd4/d4 vss pd5/d5 pvcc pd6/d6 pd7/d7 nmi res pa2/irq0 pa3/rxd pa4/txd pa5/sck pb8/irq6/a20/wait vcc pa8/irq2 vss pa9/irq3 pa0 pa1 vcc pa6/cs2 pa7/cs3 pa10/cs0 pa11/cs1 pa12/wrl pa14/rd vss pb9/irq7/a21 vcc pb7/a19 pb6/a18 pb5 pb4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 index 5 v pins note: * fwe during write mode 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 figure 1.2 SH7018 pin layout (tfp-100b: top view)
7 1.3.2 pin functions the pin functions are listed in table 1.2. table 1.2 pin functions type abbreviation i/o name function power supply v cc input power supply connect the power supply for the entire system to the v cc pin. the chip will not function if this pin is left open. v ss input ground connect this pin to a ground. connect the ground for the entire system to the v ss pin. the chip will not function if this pin is left open. pv cc input power supply for input/output circuit this pin is the power supply for an input/output circuit. clock extal input external clock connect this pin to a crystal oscillator. alternately, the extal pin may be used for external clock input. xtal input crystal connect this pin to a crystal oscillator. ck output system clock supplies the system clock signal to peripheral devices. system control res input power-on reset applying a low-level signal to this pin triggers a power-on reset. operating mode control md0 to md3 input mode setting this pin determines the operating mode. do not change the input level while the system is operating. fwp input flash memory write prevent this pin is used to prevent programming or erasing of the flash memory. interrupts nmi input non-maskable interrupt this is a non-maskable interrupt request pin. the user can select whether requests are accepted at the rising or the falling edge. irq0 to irq3 , irq6 , irq7 input interrupt request 0 to 3, 6, and 7 these are maskable interrupt request pins. level input and edge input selection are supported.
8 table 1.2 pin functions (cont) type abbreviation i/o name function address bus a0 to a21 output address bus these pins are used for address output. data bus d0 to d7 input/ output data bus this is an 8-bit bi-directional data bus. bus control cs0 to cs3 output chip select 0 to 3 these pins are used for chip select signals for external memory or devices. rd output read indicates that data is being read from an external device. wrl output write indicates that the lower eight external data bits (bits 7 to 0) are being written to. wait input wait this input is used to insert a wait cycle when accessing the external area. multifunction timer pulse unit (mtu) tioc0a tioc0c input/ output mtu input capture/output compare (channel 0) channel 0 input capture input/output compare output/pwm output pin. tioc1a tioc1b input/ output mtu input capture/output compare (channel 1) channel 1 input capture input/output compare output/pwm output pin. tioc2a tioc2b input/ output mtu input capture/output compare (channel 2) channel 2 input capture input/output compare output/pwm output pin. serial communication interface (sci) txd output transmit data transmit data output pin. rxd input receive data receive data input pin. sck input/ output serial clock clock input/output pin.
9 table 1.2 pin functions (cont) type abbreviation i/o name function a/d converter av cc input analog power supply connect to v cc potential when using an analog power supply. av ss input analog ground connect to v ss potential when using an analog power supply. an0 to an7 input analog inputs analog signal input terminals. i/o ports pa15, 14, 12 to 0 input/ output general port general i/o port pins. i/o can be specified one bit at a time. pb9 to 0 input/ output general port general i/o port pins. i/o can be specified one bit at a time. pc15 to 0 input/ output general port general i/o port pins. i/o can be specified one bit at a time. pd7 to 0 input/ output general port general i/o port pins. i/o can be specified one bit at a time. pe14 to 4, 2, 0 input/ output general port general i/o port pins. i/o can be specified one bit at a time. pf7 to 0 input general port general i/o port pins. note: the following power-on/power-off order is recommended. 1. powering on (1) turn on the 5 v power (pv cc ) first, then the 3 v power (v cc , pllv cc , av cc ). (2) pin states are undefined while only 5 v power is on, as reset input is invalid. 2. powering off (1) power off in the reverse order to powering on: turn off the 3 v power first, then the 5 v power. (2) pin states are undefined while only 5 v power is being supplied. 3. power-on/off interval to minimize the length of time during which pin states are undefined, the power-on/off interval should be kept as short as possible. also, the system design should ensure that erroneous system operation will not result from pin states becoming undefined.
10
11 section 2 cpu 2.1 register configuration the register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 general registers (rn) the sixteen 32-bit general registers (rn) are numbered r0 to r15. general registers are used for data processing and address calculation. r0 is also used as an index register. several instructions have r0 fixed as their only usable register. r15 is used as the hardware stack pointer (sp). saving and recovering the status register (sr) and program counter (pc) in exception processing is accomplished by referencing the stack using r15. figure 2.1 shows the general registers. r0 * 1 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15, sp (hardware stack pointer) * 2 0 31 1. 2. r0 functions as an index register in the indirect indexed register addressing mode and indirect indexed gbr addressing mode. in some instructions, r0 functions as a fixed source register or destination register. r15 functions as a hardware stack pointer (sp) during exception processing. notes: figure 2.1 general registers
12 2.1.2 control registers the 32-bit control registers consist of the 32-bit status register (sr), global base register (gbr), and vector base register (vbr). the status register indicates processing states. the global base register functions as a base address for the indirect gbr addressing mode to transfer data to the registers of on-chip peripheral modules. the vector base register functions as the base address of the exception processing vector area (including interrupts). figure 2.2 shows a control register. 9876543210 mqi3 i2 i1 i0 st 0 0 31 31 gbr vbr sr 31 s bit: used by the mac instruction. reserved bits. this bit always read 0. the write value should always be 0. reserved bits. this bit always read 0. the write value should always be 0. bits i0 to i3: interrupt mask bits. m and q bits: used by the div0u, div0s, and div1 instructions. global base register (gbr): indicates the base address of the indirect gbr addressing mode. the indirect gbr addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. vector base register (vbr): stores the base address of the exception processing vector area. sr: status register t bit: the movt, cmp/cond, tas, tst, bt (bt/s), bf (bf/s), sett, and clrt instructions use the t bit to indicate true (1) or false (0). the addv, addc, subv, subc, negc, div0u, div0s, div1, shar, shal, shlr, shll, rotr, rotl, rotcr, and rotcl instructions also use the t bit to indicate carry/borrow or overflow/underflow. figure 2.2 control registers
13 2.1.3 system registers system registers consist of four 32-bit registers: high and low multiply and accumulate registers (mach and macl), the procedure register (pr), and the program counter (pc). the multiply and accumulate registers store the results of multiply and accumulate operations. the procedure register stores the return address from the subroutine procedure. the program counter stores program addresses to control the flow of the processing. figure 2.3 shows a system register. macl pr pc mach 31 0 0 0 31 31 multiply and accumulate (mac) registers high and low (mach, macl): stores the results of multiply and accumulate operations. procedure register (pr): stores a return address from a subroutine procedure. program counter (pc): indicates the fourth byte (second instruction) after the current instruction. figure 2.3 system registers 2.1.4 initial values of registers table 2.1 lists the values of the registers after reset. table 2.1 initial values of registers classification register initial value general registers r0 to r14 undefined r15 (sp) value of the stack pointer in the vector address table control registers sr bits i3 to i0 are 1111 (h'f), reserved bits are 0, and other bits are undefined gbr undefined vbr h'00000000 system registers mach, macl, pr undefined pc value of the program counter in the vector address table
14 2.2 data formats 2.2.1 data format in registers register operands are always longwords (32 bits). when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4). 31 0 longword figure 2.4 longword operand 2.2.2 data format in memory memory data formats are classified into bytes, words, and longwords. byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or longword data starting from an address other than 4n. in such cases, the data accessed cannot be guaranteed. the hardware stack area, referred to by the hardware stack pointer (sp, r15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.5). 31 0 15 23 7 byte byte byte byte word word address 2n address 4n longword address m address m + 2 address m + 1 address m + 3 figure 2.5 byte, word, and longword alignment 2.2.3 immediate data format byte (8-bit) immediate data resides in an instruction code. immediate data accessed by the mov, add, and cmp/eq instructions is sign-extended and handled in registers as longword data. immediate data accessed by the tst, and, or, and xor instructions is zero-extended and handled as longword data. consequently, and instructions with immediate data always clear the upper 24 bits of the destination register.
15 word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. an immediate data transfer instruction (mov) accesses the memory table using the pc relative addressing mode with displacement. 2.3 instruction features 2.3.1 risc-type instruction set all instructions are risc type. this section details their functions. 16-bit fixed length : all instructions are 16 bits long, increasing program code efficiency. one instruction per cycle : the microprocessor can execute basic instructions in one cycle using the pipeline system. instructions are executed in 35 ns at 28.7 mhz. data length : longword is the standard data length for all operations. memory can be accessed in bytes, words, or longwords. byte or word data accessed from memory is sign-extended and handled as longword data. immediate data is sign-extended for arithmetic operations or zero- extended for logic operations. it also is handled as longword data (table 2.2). table 2.2 sign extension of word data SH7018 cpu description example of conventional cpu mov.w @(disp,pc),r1 add r1,r0 ......... .data.w h'1234 data is sign-extended to 32 bits, and r1 becomes h'00001234. it is next operated upon by an add instruction. add.w #h'1234,r0 note: @(disp, pc) accesses the immediate data. load-store architecture : basic operations are executed between registers. for operations that involve memory access, data is loaded to the registers and executed (load-store architecture). instructions such as and that manipulate bits, however, are executed directly in memory. delayed branch instructions : unconditional branch instructions are delayed. executing the instruction that follows the branch instruction and then branching reduces pipeline disruption during branching (table 2.3). there are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions.
16 table 2.3 delayed branch instructions SH7018 cpu description example of conventional cpu bra trget add r1,r0 executes an add before branching to trget add.w r1,r0 bra trget multiplication/accumulation operation : 16-bit 16-bit 32-bit multiplication operations are executed in one to two cycles. 16-bit 16-bit + 64-bit 64-bit multiplication/accumulation operations are executed in two to three cycles. 32-bit 32-bit 64-bit and 32-bit 32-bit + 64- bit 64-bit multiplication/accumulation operations are executed in two to four cycles. t bit : the t bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. the number of instructions that change the t bit is kept to a minimum to improve the processing speed (table 2.4). table 2.4 t bit SH7018 cpu description example of conventional cpu cmp/ge r1,r0 bt trget0 bf trget1 t bit is set when r0 r1. the program branches to trget0 when r0 r1 and to trget1 when r0 < r1. cmp.w r1,r0 bge trget0 blt trget1 add #1,r0 cmp/eq #0,r0 bt trget t bit is not changed by add. t bit is set when r0 = 0. the program branches if r0 = 0. sub.w #1,r0 beq trget immediate data : byte (8-bit) immediate data resides in instruction code. word or longword immediate data is not input via instruction codes but is stored in a memory table. an immediate data transfer instruction (mov) accesses the memory table using the pc relative addressing mode with displacement (table 2.5).
17 table 2.5 immediate data accessing classification SH7018 cpu example of conventional cpu 8-bit immediate mov #h'12,r0 mov.b #h'12,r0 16-bit immediate mov.w @(disp,pc),r0 ................. .data.w h'1234 mov.w #h'1234,r0 32-bit immediate mov.l @(disp,pc),r0 ................. .data.l h'12345678 mov.l #h'12345678,r0 note: @(disp, pc) accesses the immediate data. absolute address : when data is accessed by absolute address, the value already in the absolute address is placed in the memory table. loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6). table 2.6 absolute address accessing classification SH7018 cpu example of conventional cpu absolute address mov.l @(disp,pc),r1 mov.b @r1,r0 .................. .data.l h'12345678 mov.b @h'12345678,r0 note: @(disp,pc) accesses the immediate data. 16-bit/32-bit displacement : when data is accessed by 16-bit or 32-bit displacement, the pre- existing displacement value is placed in the memory table. loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). table 2.7 displacement accessing classification SH7018 cpu example of conventional cpu 16-bit displacement mov.w @(disp,pc),r0 mov.w @(r0,r1),r2 .................. .data.w h'1234 mov.w @(h'1234,r1),r2 note: @(disp,pc) accesses the immediate data.
18 2.3.2 addressing modes table 2.8 describes addressing modes and effective address calculation. table 2.8 addressing modes and effective addresses addressing mode instruction format effective addresses calculation equation direct register addressing rn the effective address is register rn. (the operand is the contents of register rn.) indirect register addressing @rn the effective address is the content of register rn. rn rn rn post-increment indirect register addressing @rn+ the effective address is the content of register rn. a constant is added to the content of rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. rn rn 1/2/4 + rn + 1/2/4 rn (after the instruction executes) byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn pre-decrement indirect register addressing @?n the effective address is the value obtained by subtracting a constant from rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. rn 1/2/4 rn 1/2/4 rn 1/2/4 byte: rn 1 rn word: rn 2 rn longword: rn 4 rn (instruction executed with rn after calculation)
19 table 2.8 addressing modes and effective addresses (cont) addressing mode instruction format effective addresses calculation equation indirect register addressing with displacement @(disp:4, rn) the effective address is rn plus a 4-bit displacement (disp). the value of disp is zero- extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. rn rn + disp 1/2/4 + 1/2/4 disp (zero-extended) byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indirect indexed register addressing @(r0, rn) the effective address is the rn value plus r0. rn r0 rn + r0 + rn + r0 indirect gbr addressing with displacement @(disp:8, gbr) the effective address is the gbr value plus an 8-bit displacement (disp). the value of disp is zero- extended, and remains the same for a byte opera- tion, is doubled for a word operation, and is quadrupled for a longword operation. gbr 1/2/4 gbr + disp 1/2/4 + disp (zero-extended) byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4
20 table 2.8 addressing modes and effective addresses (cont) addressing mode instruction format effective addresses calculation equation indirect indexed gbr addressing @(r0, gbr) the effective address is the gbr value plus the r0. gbr r0 gbr + r0 + gbr + r0 pc relative addressing with displacement @(disp:8, pc) the effective address is the pc value plus an 8-bit displacement (disp). the value of disp is zero- extended, and is doubled for a word operation, and quadrupled for a longword operation. for a longword operation, the lowest two bits of the pc value are masked. pc h'fffffffc pc + disp 2 or pc & h'fffffffc + disp 4 + 2/4 & (for longword) disp (zero-extended) word: pc + disp 2 longword: pc & h'fffffffc + disp 4
21 table 2.8 addressing modes and effective addresses (cont) addressing mode instruction format effective addresses calculation equation pc relative addressing disp:8 the effective address is the pc value sign-extended with an 8-bit displacement (disp), doubled, and added to the pc value. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 disp:12 the effective address is the pc value sign-extended with a 12-bit displacement (disp), doubled, and added to the pc value. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 rn the effective address is the register pc value plus rn. pc rn pc + rn + pc + rn immediate addressing #imm:8 the 8-bit immediate data (imm) for the tst, and, or, and xor instructions are zero-extended. #imm:8 the 8-bit immediate data (imm) for the mov, add, and cmp/eq instructions are sign-extended. #imm:8 the 8-bit immediate data (imm) for the trapa instruction is zero-extended and is quadrupled.
22 2.3.3 instruction format table 2.9 lists the instruction formats for the source operand and the destination operand. the meaning of the operand depends on the instruction code. the symbols are used as follows: ? xxxx: instruction code ? mmmm: source register ? nnnn: destination register ? iiii: immediate data ? dddd: displacement table 2.9 instruction formats instruction formats source operand destination operand example 0 format xxxx xxxx xxxx xxxx 15 0 nop n format nnnn: direct register movt rn xxxx xxxx xxxx nnnn 15 0 control register or system register nnnn: direct register sts mach,rn control register or system register nnnn: indirect pre- decrement register stc.l sr,@-rn m format mmmm: direct register control register or system register ldc rm,sr xxxx mmmm xxxx xxxx 15 0 mmmm: indirect post-increment register control register or system register ldc.l @rm+,sr mmmm: direct register jmp @rm mmmm: pc relative using rm braf rm
23 table 2.9 instruction formats (cont) instruction formats source operand destination operand example nm format mmmm: direct register nnnn: direct register add rm,rn nnnn xxxx xxxx 15 0 mmmm mmmm: direct register nnnn: indirect register mov.l rm,@rn mmmm: indirect post-increment register (multiply/ accumulate) nnnn * : indirect post-increment register (multiply/ accumulate) mach, macl mac.w @rm+,@rn+ mmmm: indirect post-increment register nnnn: direct register mov.l @rm+,rn mmmm: direct register nnnn: indirect pre- decrement register mov.l rm,@-rn mmmm: direct register nnnn: indirect indexed register mov.l rm,@(r0,rn) md format xxxx dddd 15 0 mmmm xxxx mmmmdddd: indirect register with displacement r0 (direct register) mov.b @(disp,rm),r0 nd4 format xxxx xxxx dddd 15 0 nnnn r0 (direct register) nnnndddd: indirect register with displacement mov.b r0,@(disp,rn) nmd format nnnn xxxx dddd 15 0 mmmm mmmm: direct register nnnndddd: indirect register with displacement mov.l rm,@(disp,rn) mmmmdddd: indirect register with displacement nnnn: direct register mov.l @(disp,rm),rn note: * in multiply/accumulate instructions, nnnn is the source register.
24 table 2.9 instruction formats (cont) instruction formats source operand destination operand example d format dddd xxxx 15 0 xxxx dddd dddddddd: indirect gbr with displacement r0 (direct register) mov.l @(disp,gbr),r0 r0(direct register) dddddddd: indirect gbr with displacement mov.l r0,@(disp,gbr) dddddddd: pc relative with displacement r0 (direct register) mova @(disp,pc),r0 dddddddd: pc relative bf label d12 format dddd xxxx 15 0 dddd dddd dddddddddddd: pc relative bra label (label = disp + pc) nd8 format dddd nnnn xxxx 15 0 dddd dddddddd: pc relative with displacement nnnn: direct register mov.l @(disp,pc),rn i format iiiiiiii: immediate indirect indexed gbr and.b #imm,@(r0,gbr) xxxx xxxx i i i i 15 0 i i i i iiiiiiii: immediate r0 (direct register) and #imm,r0 iiiiiiii: immediate trapa #imm ni format nnnn i i i i xxxx 15 0 i i i i iiiiiiii: immediate nnnn: direct register add #imm,rn
25 2.4 instruction set by classification table 2.10 classification of instructions classification types operation code function no. of instructions data transfer 5 mov data transfer, immediate data transfer, peripheral module data transfer, structure data transfer 39 mova effective address transfer movt t bit transfer swap swap of upper and lower bytes xtrct extraction of the middle of registers connected arithmetic 21 add binary addition 33 operations addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s initialization of signed division div0u initialization of unsigned division dmuls signed double-length multiplication dmulu unsigned double-length multiplication dt decrement and test exts sign extension extu zero extension mac multiply/accumulate, double-length multiply/accumulate operation mul double-length multiply operation muls signed multiplication mulu unsigned multiplication neg negation negc negation with borrow sub binary subtraction subc binary subtraction with borrow subv binary subtraction with underflow
26 table 2.10 classification of instructions (cont) classification types operation code function no. of instructions logic 6 and logical and 14 operations not bit inversion or logical or tas memory test and bit set tst logical and and t bit set xor exclusive or shift 10 rotl one-bit left rotation 14 rotr one-bit right rotation rotcl one-bit left rotation with t bit rotcr one-bit right rotation with t bit shal one-bit arithmetic left shift shar one-bit arithmetic right shift shll one-bit logical left shift shlln n-bit logical left shift shlr one-bit logical right shift shlrn n-bit logical right shift branch 9 bf conditional branch, conditional branch with delay (branch when t = 0) 11 bt conditional branch, conditional branch with delay (branch when t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure rts return from subroutine procedure
27 table 2.10 classification of instructions (cont) classification types operation code function no. of instructions system 11 clrt t bit clear 31 control clrmac mac register clear ldc load to control register lds load to system register nop no operation rte return from exception processing sett t bit set sleep shift into power-down mode stc storing control register data sts storing system register data trapa trap exception processing total: 62 142 table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and execution states in order by classification.
28 table 2.11 instruction code format item format explanation instruction op.sz src,dest op: operation code sz: size (b: byte, w: word, or l: longword) src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement * 1 instruction code msb ? lsb mmmm: source register nnnn: destination register 0000: r0 0001: r1 . . . 1111: r15 iiii: immediate data dddd: displacement operation , direction of transfer (xx) memory operand m/q/t flag bits in the sr & logical and of each bit | logical or of each bit ^ exclusive or of each bit ~ logical not of each bit <>n n-bit right shift execution cycles ? value when no wait states are inserted * 2 t bit ? value of t bit after instruction is executed. an em-dash ( ? ) in the column means no change. notes: 1. depending on the operand size, displacement is scaled 1, 2, or 4. for details, see the sh-1/sh-2/sh-dsp programming manual . 2. instruction execution cycles: the execution cycles shown in the table are minimums. the actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same.
29 table 2.12 data transfer instructions instruction instruction code operation execu- tion cycles t bit mov #imm,rn 1110nnnniiiiiiii #imm sign extension rn 1 mov.w @(disp,pc),rn 1001nnnndddddddd (disp 2 + pc) sign extension rn 1 mov.l @(disp,pc),rn 1101nnnndddddddd (disp 4 + pc) rn 1 mov rm,rn 0110nnnnmmmm0011 rm rn 1 mov.b rm,@rn 0010nnnnmmmm0000 rm (rn) 1 mov.w rm,@rn 0010nnnnmmmm0001 rm (rn) 1 mov.l rm,@rn 0010nnnnmmmm0010 rm (rn) 1 mov.b @rm,rn 0110nnnnmmmm0000 (rm) sign extension rn 1 mov.w @rm,rn 0110nnnnmmmm0001 (rm) sign extension rn 1 mov.l @rm,rn 0110nnnnmmmm0010 (rm) rn 1 mov.b rm,@?n 0010nnnnmmmm0100 rn 1 rn, rm (rn) 1 mov.w rm,@?n 0010nnnnmmmm0101 rn 2 rn, rm (rn) 1 mov.l rm,@?n 0010nnnnmmmm0110 rn 4 rn, rm (rn) 1 mov.b @rm+,rn 0110nnnnmmmm0100 (rm) sign extension rn,rm + 1 rm 1 mov.w @rm+,rn 0110nnnnmmmm0101 (rm) sign extension rn,rm + 2 rm 1 mov.l @rm+,rn 0110nnnnmmmm0110 (rm) rn,rm + 4 rm 1 mov.b r0,@(disp,rn) 10000000nnnndddd r0 (disp + rn) 1 mov.w r0,@(disp,rn) 10000001nnnndddd r0 (disp 2 + rn) 1 mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm (disp 4 + rn) 1 mov.b @(disp,rm),r0 10000100mmmmdddd (disp + rm) sign extension r0 1 mov.w @(disp,rm),r0 10000101mmmmdddd (disp 2 + rm) sign extension r0 1 mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp 4 + rm) rn 1 mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm (r0 + rn) 1
30 table 2.12 data transfer instructions (cont) instruction instruction code operation execu- tion cycles t bit mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm (r0 + rn) 1 mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm (r0 + rn) 1 mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0 + rm) sign extension rn 1 mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0 + rm) sign extension rn 1 mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0 + rm) rn 1 mov.b r0,@(disp,gbr) 11000000dddddddd r0 (disp + gbr) 1 mov.w r0,@(disp,gbr) 11000001dddddddd r0 (disp 2 + gbr) 1 mov.l r0,@(disp,gbr) 11000010dddddddd r0 (disp 4 + gbr) 1 mov.b @(disp,gbr),r0 11000100dddddddd (disp + gbr) sign extension r0 1 mov.w @(disp,gbr),r0 11000101dddddddd (disp 2 + gbr) sign extension r0 1 mov.l @(disp,gbr),r0 11000110dddddddd (disp 4 + gbr) r0 1 mova @(disp,pc),r0 11000111dddddddd disp 4 + pc r0 1 movt rn 0000nnnn00101001 t rn 1 swap.b rm,rn 0110nnnnmmmm1000 rm swap the bottom two bytes rn 1 swap.w rm,rn 0110nnnnmmmm1001 rm swap two consecutive words rn 1 xtrct rm,rn 0010nnnnmmmm1101 rm: middle 32 bits of rn rn 1
31 table 2.13 arithmetic operation instructions instruction instruction code operation execu- tion cycles t bit add rm,rn 0011nnnnmmmm1100 rn + rm rn 1 add #imm,rn 0111nnnniiiiiiii rn + imm rn 1 addc rm,rn 0011nnnnmmmm1110 rn + rm + t rn, carry t 1 carry addv rm,rn 0011nnnnmmmm1111 rn + rm rn, overflow t 1 overflow cmp/eq #imm,r0 10001000iiiiiiii if r0 = imm, 1 t 1 comparison result cmp/eq rm,rn 0011nnnnmmmm0000 if rn = rm, 1 t 1 comparison result cmp/hs rm,rn 0011nnnnmmmm0010 if rn rm with unsigned data, 1 t 1 comparison result cmp/ge rm,rn 0011nnnnmmmm0011 if rn rm with signed data, 1 t 1 comparison result cmp/hi rm,rn 0011nnnnmmmm0110 if rn > rm with unsigned data, 1 t 1 comparison result cmp/gt rm,rn 0011nnnnmmmm0111 if rn > rm with signed data, 1 t 1 comparison result cmp/pl rn 0100nnnn00010101 if rn > 0, 1 t 1 comparison result cmp/pz rn 0100nnnn00010001 if rn 0, 1 t 1 comparison result cmp/str rm,rn 0010nnnnmmmm1100 if rn and rm have an equivalent byte, 1 t 1 comparison result div1 rm,rn 0011nnnnmmmm0100 single-step division (rn/rm) 1 calculation result div0s rm,rn 0010nnnnmmmm0111 msb of rn q, msb of rm m, m ^ q t 1 calculation result div0u 0000000000011001 0 m/q/t 1 0
32 table 2.13 arithmetic operation instructions (cont) instruction instruction code operation execu- tion cycles t bit dmuls.l rm,rn 0011nnnnmmmm1101 signed operation of rn rm mach, macl 32 32 64 bit 2 to 4 * dmulu.l rm,rn 0011nnnnmmmm0101 unsigned operation of rn rm mach, macl 32 32 64 bit 2 to 4 * dt rn 0100nnnn00010000 rn e 1 rn, when rn is 0, 1 t. when rn is nonzero, 0 t 1 comparison result exts.b rm,rn 0110nnnnmmmm1110 a byte in rm is sign- extended rn 1 ? exts.w rm,rn 0110nnnnmmmm1111 a word in rm is sign- extended rn 1 ? extu.b rm,rn 0110nnnnmmmm1100 a byte in rm is zero- extended rn 1 ? extu.w rm,rn 0110nnnnmmmm1101 a word in rm is zero- extended rn 1 ? mac.l @rm+,@rn+ 0000nnnnmmmm1111 signed operation of (rn) (rm) + mac mac 32 32 64 bit 3/(2 to 4) * mac.w @rm+,@rn+ 0100nnnnmmmm1111 signed operation of (rn) (rm) + mac mac 16 16 + 64 64 bit 3/(2) * mul.l rm,rn 0000nnnnmmmm0111 rn rm macl, 32 32 32 bit 2 to 4 * muls.w rm,rn 0010nnnnmmmm1111 signed operation of rn rm mac 16 16 32 bit 1 to 3 * mulu.w rm,rn 0010nnnnmmmm1110 unsigned operation of rn rm mac 16 16 32 bit 1 to 3 * neg rm,rn 0110nnnnmmmm1011 0 e rm rn 1 ? negc rm,rn 0110nnnnmmmm1010 0 e rm e t rn, borrow t 1 borrow
33 table 2.13 arithmetic operation instructions (cont) instruction instruction code operation execu- tion cycles t bit sub rm,rn 0011nnnnmmmm1000 rn rm rn 1 subc rm,rn 0011nnnnmmmm1010 rn rm t rn, borrow t 1 borrow subv rm,rn 0011nnnnmmmm1011 rn rm rn, underflow t 1 overflow note: * the normal minimum number of execution cycles. (the number in parentheses is the number of cycles when there is contention with following instructions.) table 2.14 logic operation instructions instruction instruction code operation execu- tion cycles t bit and rm,rn 0010nnnnmmmm1001 rn & rm rn 1 and #imm,r0 11001001iiiiiiii r0 & imm r0 1 and.b #imm,@(r0,gbr) 11001101iiiiiiii (r0 + gbr) & imm (r0 + gbr) 3 not rm,rn 0110nnnnmmmm0111 ~rm rn 1 or rm,rn 0010nnnnmmmm1011 rn | rm rn 1 or #imm,r0 11001011iiiiiiii r0 | imm r0 1 or.b #imm,@(r0,gbr) 11001111iiiiiiii (r0 + gbr) | imm (r0 + gbr) 3 tas.b @rn 0100nnnn00011011 if (rn) is 0, 1 t; 1 msb of (rn) 4 test result tst rm,rn 0010nnnnmmmm1000 rn & rm; if the result is 0, 1 t 1 test result tst #imm,r0 11001000iiiiiiii r0 & imm; if the result is 0, 1 t 1 test result tst.b #imm,@(r0,gbr) 11001100iiiiiiii (r0 + gbr) & imm; if the result is 0, 1 t 3 test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm rn 1 xor #imm,r0 11001010iiiiiiii r0 ^ imm r0 1 xor.b #imm,@(r0,gbr) 11001110iiiiiiii (r0 + gbr) ^ imm (r0 + gbr) 3
34 table 2.15 shift instructions instruction instruction code operation execu- tion cycles t bit rotl rn 0100nnnn00000100 t rn msb 1 msb rotr rn 0100nnnn00000101 lsb rn t 1 lsb rotcl rn 0100nnnn00100100 t rn t 1 msb rotcr rn 0100nnnn00100101 t rn t 1 lsb shal rn 0100nnnn00100000 t rn 0 1 msb shar rn 0100nnnn00100001 msb rn t 1 lsb shll rn 0100nnnn00000000 t rn 0 1 msb shlr rn 0100nnnn00000001 0 rn t 1 lsb shll2 rn 0100nnnn00001000 rn<<2 rn 1 shlr2 rn 0100nnnn00001001 rn>>2 rn 1 shll8 rn 0100nnnn00011000 rn<<8 rn 1 shlr8 rn 0100nnnn00011001 rn>>8 rn 1 shll16 rn 0100nnnn00101000 rn<<16 rn 1 shlr16 rn 0100nnnn00101001 rn>>16 rn 1
35 table 2.16 branch instructions instruction instruction code operation exec. cycles t bit bf label 10001011dddddddd if t = 0, disp 2 + pc pc; if t = 1, nop 3/1 * bf/s label 10001111dddddddd delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop 3/1 * bt label 10001001dddddddd if t = 1, disp 2 + pc pc; if t = 0, nop 3/1 * bt/s label 10001101dddddddd delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop 2/1 * bra label 1010dddddddddddd delayed branch, disp 2 + pc pc 2 ? braf rm 0000mmmm00100011 delayed branch, rm + pc pc 2 ? bsr label 1011dddddddddddd delayed branch, pc pr, disp 2 + pc pc 2 ? bsrf rm 0000mmmm00000011 delayed branch, pc pr, rm + pc pc 2 ? jmp @rm 0100mmmm00101011 delayed branch, rm pc 2 ? jsr @rm 0100mmmm00001011 delayed branch, pc pr, rm pc 2 ? rts 0000000000001011 delayed branch, pr pc 2 ? note: * one state when it does not branch.
36 table 2.17 system control instructions instruction instruction code operation exec. cycles t bit clrt 0000000000001000 0 t10 clrmac 0000000000101000 0 mach, macl 1 ldc rm,sr 0100mmmm00001110 rm sr 1 lsb ldc rm,gbr 0100mmmm00011110 rm gbr 1 ldc rm,vbr 0100mmmm00101110 rm vbr 1 ldc.l @rm+,sr 0100mmmm00000111 (rm) sr, rm + 4 rm 3 lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) gbr, rm + 4 rm 3 ldc.l @rm+,vbr 0100mmmm00100111 (rm) vbr, rm + 4 rm 3 lds rm,mach 0100mmmm00001010 rm mach 1 lds rm,macl 0100mmmm00011010 rm macl 1 lds rm,pr 0100mmmm00101010 rm pr 1 lds.l @rm+,mach 0100mmmm00000110 (rm) mach, rm + 4 rm 1 lds.l @rm+,macl 0100mmmm00010110 (rm) macl, rm + 4 rm 1 lds.l @rm+,pr 0100mmmm00100110 (rm) pr, rm + 4 rm 1 nop 0000000000001001 no operation 1 rte 0000000000101011 delayed branch, stack area pc/sr 4 sett 0000000000011000 1 t11 sleep 0000000000011011 sleep 3 * stc sr,rn 0000nnnn00000010 sr rn 1 stc gbr,rn 0000nnnn00010010 gbr rn 1 stc vbr,rn 0000nnnn00100010 vbr rn 1 stc.l sr,@?n 0100nnnn00000011 rn 4 rn, sr (rn) 2 stc.l gbr,@?n 0100nnnn00010011 rn 4 rn, gbr (rn) 2 stc.l vbr,@?n 0100nnnn00100011 rn 4 rn, br (rn) 2 sts mach,rn 0000nnnn00001010 mach rn 1 sts macl,rn 0000nnnn00011010 macl rn 1 sts pr,rn 0000nnnn00101010 pr rn 1
37 table 2.17 system control instructions (cont) instruction instruction code operation exec. cycles t bit sts.l mach,@?n 0100nnnn00000010 rn 4 rn, mach (rn) 1 sts.l macl,@?n 0100nnnn00010010 rn 4 rn, macl (rn) 1 sts.l pr,@?n 0100nnnn00100010 rn 4 rn, pr (rn) 1 trapa #imm 11000011iiiiiiii pc/sr stack area, (imm) pc 8 note: * the number of execution cycles before the chip enters sleep mode: the execution cycles shown in the table are minimums. the actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same.
38 2.5 processing states 2.5.1 state transitions the cpu has for processing states: reset, exception processing, program execution, and power- down. figure 2.6 shows the transitions between the states. from all states when res= 0 power-on reset state program execution state sleep mode standby mode exception processing state interrupt triggered exception processing triggered exception processing ends nmi interrupt triggered reset state power-down state res= 1 sleep instruction when sby bit set sleep instruction when sby bit cleared figure 2.6 transitions between processing states reset state: the cpu resets in this state. when the res pin goes low, a power-on reset results. exception processing state: this is a transient state that occurs when the cpu? processing state flow is altered due to the triggering of exception processing. in the case of a reset, the execution start address and stack pointer (sp) initial value are fetched from the exception processing vector table as the initial values of the program counter (pc) and stored. the cpu then branches to the execution start address and execution of the program begins.
39 in the case of an interrupt or the like, the sp is accessed and the pc and status register (sr) are saved to the stack area. the exception service routine start address is fetched from the exception processing vector table. the cpu then branches to that address and execution of the program begins. the processing state which follows is the program execution state. program execution state: in this state the cpu executes programs sequentially. power-down state: in this state cpu operation halts in order to consume less power. the sleep instruction causes the cpu to enter the power-down state. this state has two modes, the sleep mode and the standby mode. 2.5.2 power-down state the power-down state is one of the cpu? processing states. in this state cpu operation halts, in addition to the execution of programs, and power consumption is reduced. it has two modes, the sleep mode and the standby mode. sleep mode: issuing the sleep instruction when the standby bit (sby) of standby control register (sbycr) is cleared to 0 causes the cpu to enter the sleep mode. in the sleep mode cpu operation is halted, but data stored in the cpu? internal registers and in on-chip ram is retained. the functions of on-chip peripheral modules other than the cpu do not halt. a power-on reset or any interrupt causes the cpu to recover from the sleep mode. exception processing then takes place, after which the cpu enters the normal program execution mode. standby mode: issuing the sleep instruction when sby of sbycr is set to 1 causes the cpu to enter the standby mode. in the standby mode the functioning of the cpu, on-chip peripheral modules, and oscillator are halted. if the chip enters the standby mode while a multiplier instruction is executing, the mach and macl values become uncertain. a power-on reset or nmi interrupt causes the chip to recover from the sleep mode. after a reset the oscillator stabilization time elapses, after which exception processing takes place and then the chip enters the normal program execution mode. in the case of an nmi interrupt, the oscillator stabilization time must elapse, after which exception processing takes place and then the chip enters the normal program execution mode. this mode halts the operation of the oscillator, so power consumption is decreased substantially.
40 table 2.18 power-down state state mode transition conditions clock cpu on-chip peripheral modules contents of cpu registers contents of on-chip ram i/o port pin states recovery method sleep mode sleep command issued when sby of sbycr is cleared to 0 operating halted operating retained retained retained (1) interrupt (2) power-on reset standby mode sleep command issued when sby of sbycr is set to 1 halted halted halted or initialized * retained retained retained or hi-z (can be specified by user) (1) nmi interrupt (2) power-on reset note: * differs depending on the peripheral module and pin.
41 section 3 operating modes 3.1 operating mode selection the SH7018 has four operating modes: mcu mode, boot mode, user program mode, and programmer mode. the settings of the mode pins (md3 to md0) determine the mode in which the chip operates. the mode pin settings must not be changed while the chip is operating (while power is being supplied). the method of selecting the operating mode is shown in table 3.1. table 3.1 operating mode selection pin settings fwp md3 * 1 md2 * 1 md1 md0 operating mode on-chip rom cs0 bus width 10010 mcu mode enabled 8 bits * 2 00000 boot mode * 1 enabled 8 bits * 2 00010 user program mode * 1 enabled 8 bits * 2 11101 programmer mode * 1 enabled notes: 1. f-ztat version only. 2. set using bcr1 of bsc. 3.2 description of operating modes mcu mode: the on-chip rom is enabled in the mcu mode. the bus width for the on-chip rom space is 32 bits. boot mode: refer to section 16.6.1 boot mode for information on the boot mode. user program mode: refer to section 16.6.2 user program mode for information on the user program mode. programmer mode: refer to section 16.11 flash memory programmer mode for information on the programmer mode.
42 3.3 pin configuration the functions of the pins relating to the operating modes are shown in table 3.2. table 3.2 pin functions pin name i/o function xtal input connected to the crystal resonator. extal input connected to the crystal resonator, or used as input pin for external clock. md0 input the level at this pin is used in the operating mode specification. md1 input the level at this pin is used in the operating mode specification. md2 input the level at this pin is used in the operating mode specification. md3 input the level at this pin is used in the operating mode specification.
43 section 4 clock pulse generator (cpg) 4.1 overview the clock pulse generator (cpg) supplies clock pulses within the SH7018 and to external devices. the SH7018? cpg operates the SH7018 at a frequency equal to the oscillation frequency of the crystal resonator. the cpg is composed of an oscillator and a duty adjustment circuit (figure 4.1). there are two ways of generating a clock with the cpg: by connecting a crystal resonator, or by inputting an external clock. extal cpg xtal internal clock ( ) oscillator duty adjustment circuit ck (system clock) figure 4.1 cpg block diagram 4.2 clock source either a crystal resonator or an external clock can be selected as the clock pulse source. 4.2.1 crystal resonator connection circuit configuration: figure 4.2 shows the method of connecting a crystal resonator. use the damping resistance (rd) shown in table 4.1. an at-cut parallel-resonance type crystal resonator with the same frequency as the system clock (ck) should be used. load capacitors (c l1 , c l2 ) must be connected as shown in the figure. the clock pulses generated by the crystal resonator and internal oscillator are sent to the duty adjustment circuit. after the duty has been adjusted, the pulses are supplied within the SH7018 chip and to external devices.
44 extal xtal cl1 cl2 rd cl1 = cl2 = 18 to 22 figure 4.2 example of crystal resonator connection table 4.1 damping resistance value frequency (mhz) 20 rd ( ? )0 crystal resonator: figure 4.3 shows an equivalent circuit for the crystal resonator. use a crystal resonator with the characteristics shown in table 4.2. xtal l cl co rs extal figure 4.3 crystal resonator equivalent circuit table 4.2 crystal resonator characteristics frequency (mhz) parameter 20 rs max ( ? )60 co max (pf) 7
45 4.2.2 external clock input input the external clock to the extal pin and leave the xtal pin open (figure 4.4.). the external clock frequency should be the same as that of the system clock (ck). xtal open extal external clock input figure 4.4 external clock input 4.3 usage notes note on board design: place the crystal resonator and load capacitors as close as possible to the extal and xtal pins. to prevent induction from interfering with correct oscillation, ensure that other signal lines to not cross the extal and xtal pin signal lines. xtal SH7018 extal avoid crossing signal lines c l2 c l1 figure 4.5 note on board design
46 notes on duty adjustment: duty adjustment circuit is performed on an input clock of 5 mhz or higher. with a frequency of less than 5 mhz, duty adjustment may not be performed, but ac characteristics t ch (clock high-level width) and t cl (clock low-level width) are satisfied, and there is no problem with SH7018 internal operation. figure 4.6 shows the basic characteristics of the duty adjustment circuit. the duty adjustment circuit does not correct for transient fluctuations or jitter in the input clock. thus, several tens of ? are required until duty adjustment is performed and a stable clock is obtained. 30 40 50 60 70 70 60 50 40 30 output duty (%) 15 input duty input frequency (mhz) 21020 figure 4.6 duty adjustment circuit characteristics
47 section 5 exception processing 5.1 overview 5.1.1 types of exception processing and priority exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. when several exception processing sources occur at once, they are processed according to the priority shown. table 5.1 types of exception processing and priority order exception source priority reset power-on reset high address error cpu address error interrupt nmi irq on-chip peripheral modules: ? multifunction timer/pulse unit (mtu) ? serial communications interface (sci) ? a/d converter (a/d) ? compare match timer (cmt) ? watchdog timer (wdt) ? 8-bit timer 2 (tim2) instructions trap instruction (trapa instruction) general illegal instructions (undefined code) illegal slot instructions (undefined code placed directly after a delay branch instruction * 1 or instructions that rewrite the pc * 2 ) low notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf. 2. instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf.
48 5.1.2 exception processing operations the exception processing sources are detected and begin processing according to the timing shown in table 5.2. table 5.2 timing of exception source detection and the start of exception processing exception source timing of source detection and start of processing power-on reset starts when the res pin changes from low to high. address error detected when instruction is decoded and starts when the previous executing instruction finishes executing. interrupts detected when instruction is decoded and starts when the previous executing instruction finishes executing. instructions trap instruction starts from the execution of a trapa instruction. general illegal instructions starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). illegal slot instructions starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the pc. when exception processing starts, the cpu operates as follows: 1. exception processing triggered by reset: the initial values of the program counter (pc) and stack pointer (sp) are fetched from the exception processing vector table (pc and sp are respectively the h'00000000 and h'00000004 addresses). see section 5.1.3, exception processing vector table, for more information. 0 is then written to the vector base register (vbr) and 1111 is written to the interrupt mask bits (i3 to i0) of the status register (sr). the program begins running from the pc address fetched from the exception processing vector table. 2. exception processing triggered by address errors, interrupts and instructions: sr and pc are saved to the stack indicated by r15. for interrupt exception processing, the interrupt priority level is written to the sr? interrupt mask bits (i3 to i0). for address error and instruction exception processing, the i3 to i0 bits are not affected. the start address is then fetched from the exception processing vector table and the program begins running from that address.
49 5.1.3 exception processing vector table before exception processing begins running, the exception processing vector table must be set in memory. the exception processing vector table stores the start addresses of exception service routines. (the reset exception processing table holds the initial values of pc and sp.) all exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. during exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which indicated by this vector table address. table 5.3 shows the vector numbers and vector table address offsets. table 5.4 shows how vector table addresses are calculated. table 5.3 exception processing vector table exception sources vector numbers vector table address offset power-on reset pc 0 h'00000000 to h'00000003 sp 1 h'00000004 to h'00000007 (reserved by system) 2 h'00000008 to h'0000000f 3 general illegal instruction 4 h'00000010 to h'00000013 (reserved by system) 5 h'00000014 to h'00000017 slot illegal instruction 6 h'00000018 to h'0000001b (reserved by system) 7 h'0000001c to h'0000001f (reserved by system) 8 h'00000020 to h'00000023 cpu address error 9 h'00000024 to h'00000027 (reserved by system) 10 h'00000028 to h'0000002b interrupts nmi 11 h'0000002c to h'0000002f (reserved by system) 12 : 31 h'00000030 to h'00000033 : h'0000007c to h'0000007f trap instruction (user vector) 32 : 63 h'00000080 to h'00000083 : h'000000fc to h'000000ff
50 table 5.3 exception processing vector table (cont) exception sources vector numbers vector table address offset interrupts irq0 64 h'00000100 to h'00000103 irq1 65 h'00000104 to h'00000107 irq2 66 h'00000108 to h'0000010b irq3 67 h'0000010c to h'0000010f (reserved by system) 68 h'00000110 to h'00000113 69 h'00000114 to h'00000117 interrupts irq6 70 h'00000118 to h'0000011b irq7 71 h'0000011c to h'0000011f on-chip peripheral module * 72 : 255 h'00000120 to h'00000124 : h'000003fc to h'000003ff note: * the vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, interrupt controller, table 6.3, interrupt exception processing vectors and priorities. table 5.4 calculating exception processing vector table addresses exception source vector table address calculation resets vector table address = (vector table address offset) = (vector number) 4 address errors, interrupts, instructions vector table address = vbr + (vector table address offset) = vbr + (vector number) 4 notes: 1. vbr: vector base register 2. vector table address offset: see table 5.3. 3. vector number: see table 5.3.
51 5.2 resets 5.2.1 reset a reset has the highest priority of any exception source. as shown in table 5.5, a power-on reset initializes the internal state of the cpu and the on-chip peripheral module registers. table 5.5 types of resets conditions for transition to reset status internal status type res cpu on-chip peripheral module power-on reset low initialized initialized 5.2.2 power-on reset when the res pin is driven low, the lsi does a power-on reset. to reliably reset the lsi, the res pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 20 t cyc (when the clock circuit is running). during power-on reset, cpu internal status and all registers of on-chip peripheral modules are initialized. see appendix b, pin status, for the status of individual pins during the power-on reset status. in the power-on reset status, power-on reset exception processing starts when the res pin is first driven low for a set period of time and then returned to high. the cpu will then operate as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception processing vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception processing vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3 to i0) of the status register (sr) are set to h'f (1111). 4. the values fetched from the exception processing vector table are set in the program counter (pc) and sp and the program begins executing. be certain to always perform power-on reset processing when turning the system power on.
52 5.3 address errors address errors occur when instructions are fetched or data read or written, as shown in table 5.6. table 5.6 bus cycles and address errors bus cycle type bus cycle description address errors instruction fetch instruction fetched from even address none (normal) instruction fetched from odd address address error occurs instruction fetched from other than on-chip peripheral module space * none (normal) instruction fetched from on-chip peripheral module space * address error occurs data read/write word data accessed from even address none (normal) word data accessed from odd address address error occurs longword data accessed from other than a longword boundary address error occurs byte or word data accessed in on-chip peripheral module space * none (normal) longword data accessed in 16-bit on-chip peripheral module space * none (normal) longword data accessed in 8-bit on-chip peripheral module space * address error occurs note: * see section 7, bus state controller. 5.3.1 address error exception processing when an address error occurs, the bus cycle in which the address error occurred ends. when the executing instruction then finishes, address error exception processing starts up. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the last executed instruction. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. the jump that occurs is not a delayed branch.
53 5.4 interrupts table 5.7 shows the sources that start up interrupt exception processing. these are divided into nmi, irq and on-chip peripheral modules. table 5.7 interrupt sources type request source number of sources nmi nmi pin (external input) 1 irq irq0 to irq3 , irq6 , irq7 (external input) 6 on-chip peripheral module multifunction timer/pulse unit (mtu) 11 serial communications interface (sci) 4 a/d converter 1 compare match timer (cmt) 2 watchdog timer (wdt) 1 8-bit timer 2 (tim2) 1 each interrupt source is allocated a different vector number and vector table offset. see section 6, interrupt controller, table 6.3, interrupt exception processing vectors and priorities, for more information on vector numbers and vector table address offsets. 5.4.1 interrupt priority level the interrupt priority order is predetermined. when multiple interrupts occur simultaneously (overlap), the interrupt controller (intc) determines their relative priorities and starts up processing according to the results. the priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. the nmi interrupt has priority 16 and cannot be masked, so it is always accepted. the user break interrupt priority level is 15. irq interrupts and on-chip peripheral module interrupt priority levels can be set freely using the intc? interrupt priority level setting registers a through h (ipra to iprh) as shown in table 5.8. the priority levels that can be set are 0 to 15. level 16 cannot be set. see section 6.3.1, interrupt priority registers a to h (ipra to iprh), for more information on ipra to iprh.
54 table 5.8 interrupt priority order type priority level comment nmi 16 fixed priority level. cannot be masked. irq 0 to 15 set with interrupt priority level setting registers a through h (ipra to iprh). on-chip peripheral module 0 to 15 set with interrupt priority level setting registers a through h (ipra to iprh). 5.4.2 interrupt exception processing when an interrupt occurs, its priority level is ascertained by the interrupt controller (intc). nmi is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (i3 to i0) of the status register (sr). when an interrupt is accepted, exception processing begins. in interrupt exception processing, the cpu saves sr and the program counter (pc) to the stack. the priority level value of the accepted interrupt is written to sr bits i3 to i0. for nmi, however, the priority level is 16, but the value set in i3 to i0 is h'f (level 15). next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. see section 6.4, interrupt operation, for more information on the interrupt exception processing. 5.5 exceptions triggered by instructions exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.9. table 5.9 types of exceptions triggered by instructions type source instruction comment trap instructions trapa illegal slot instructions undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the pc delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf general illegal instructions undefined code anywhere besides in a delay slot
55 5.5.1 trap instructions when a trapa instruction is executed, trap instruction exception processing starts up. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the trapa instruction. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the trapa instruction. that address is jumped to and the program starts executing. the jump that occurs is not a delayed branch. 5.5.2 illegal slot instructions an instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. when the instruction placed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. illegal slot exception processing also starts up when an instruction that rewrites the program counter (pc) is placed in a delay slot. the processing starts when the instruction is decoded. the cpu handles an illegal slot instruction as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the pc. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that occurred. that address is jumped to and the program starts executing. the jump that occurs is not a delayed branch. 5.5.3 general illegal instructions when undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. the cpu handles general illegal instructions the same as illegal slot instructions. unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code.
56 5.6 when exception sources are not accepted when an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. when this happens, it will be accepted when an instruction that can accept the exception is decoded. table 5.10 generation of exception sources immediately after a delayed branch instruction or interrupt-disabled instruction exception source point of occurrence address error interrupt immediately after a delayed branch instruction * 1 not accepted not accepted immediately after an interrupt-disabled instruction * 2 accepted not accepted notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf 2. interrupt-disabled instructions: ldc, ldc.l, stc, stc.l, lds, lds.l, sts, sts.l 5.6.1 immediately after a delayed branch instruction when an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. the delayed branch instruction and the instruction located immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 immediately after an interrupt-disabled instruction when an instruction immediately following an interrupt-disabled instruction is decoded, interrupts are not accepted. address errors are accepted.
57 5.7 stack status after exception processing ends the status of the stack after exception processing ends is as shown in table 5.11. table 5.11 types of stack status after exception processing ends types stack status address error 32 bits 32 bits sr address of instruction after executed instruction sp trap instruction 32 bits 32 bits sr address of instruction after trapa instruction sp general illegal instruction 32 bits 32 bits sr start address of illegal instruction sp interrupt 32 bits 32 bits sr address of instruction after executed instruction sp illegal slot instruction 32 bits 32 bits sr jump destination address of delay branch instruction sp
58 5.8 notes on use 5.8.1 value of stack pointer (sp) the value of the stack pointer must always be a multiple of four. if it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 value of vector base register (vbr) the value of the vector base register must always be a multiple of four. if it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 address errors caused by stacking of address error exception processing when the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. address errors will then also occur in the stacking for this address error exception processing. to ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. this allows program control to be shifted to the address error exception service routine and enables error processing. when an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. during stacking of the status register (sr) and program counter (pc), the sp is ? for both, so the value of sp will not be a multiple of four after the stacking either. the address value output during stacking is the sp value, so the address where the error occurred is itself output. this means the write data stacked will be undefined.
59 section 6 interrupt controller (intc) 6.1 overview the interrupt controller (intc) ascertains the priority of interrupt sources and controls interrupt requests to the cpu. the intc has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 features the intc has the following features: ? 16 levels of interrupt priority: by setting the eight interrupt-priority level registers, the priorities of irq interrupts and on-chip peripheral module interrupts can be set in 16 levels for different request sources. ? nmi noise canceler function: nmi input level bits indicate the nmi pin status. by reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler.
60 6.1.2 block diagram figure 6.1 is a block diagram of the intc. cpu sr interrupt request com- parator priority ranking judg- ment cpu input control (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) isr icr ipr ipra to iprh module bus bus interface internal bus i3 i2 i1 i0 intc nmi irq0 irq1 irq2 irq3 irq6 irq7 mtu cmt sci1 a/d wdt (interrupt request) tim2 mtu: cmt: sci1: a/d: wdt: tim2: icr: isr: ipra to iprh: sr: interrupt control register irq ststus register interrupt priority level setting registers a to h status register multifunction timer pulse unit compare match timer serial communication interface a/d converter watchdog timer 8-bit timer figure 6.1 intc block diagram
61 6.1.3 pin configuration table 6.1 shows the intc pin configuration. table 6.1 pin configuration name abbreviation i/o function non-maskable interrupt input pin nmi i input of non-maskable interrupt request signal interrupt request input pins irq0 to irq3 , irq6 , irq7 i input of maskable interrupt request signals 6.1.4 register configuration the intc has the 10 registers shown in table 6.2. these registers set the priority of the interrupts and control external interrupt input signal detection. table 6.2 register configuration name abbr. r/w initial value address access sizes interrupt priority register a ipra r/w h'0000 h'ffff8348 8, 16, 32 interrupt priority register b iprb r/w h'0000 h'ffff834a 8, 16, 32 interrupt priority register c iprc r/w h'0000 h'ffff834c 8, 16, 32 interrupt priority register d iprd r/w h'0000 h'ffff834e 8, 16, 32 interrupt priority register e ipre r/w h'0000 h'ffff8350 8, 16, 32 interrupt priority register f iprf r/w h'0000 h'ffff8352 8, 16, 32 interrupt priority register g iprg r/w h'0000 h'ffff8354 8, 16, 32 interrupt priority register h iprh r/w h'0000 h'ffff8356 8, 16, 32 interrupt control register icr r/w * 1 h'ffff8358 8, 16, 32 irq status register isr r(w) * 2 h'0000 h'ffff835a 8, 16, 32 notes: 1. the value when the nmi pin is high is h'8000; when the nmi pin is low, it is h'0000. 2. only 0 can be written, in order to clear flags.
62 6.2 interrupt sources there are three types of interrupt sources: nmi, irq, and on-chip peripheral modules. each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). giving an interrupt a priority level of 0 masks it. 6.2.1 nmi interrupts the nmi interrupt has priority 16 and is always accepted. input at the nmi pin is detected by edge. use the nmi edge select bit (nmie) in the interrupt control register (icr) to select either the rising or falling edge. nmi interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to level 15. 6.2.2 irq interrupts irq interrupts are requested by input from pins irq0 to irq3 , irq6 , and irq7 . set the irq sense select bits (irq0s to irq3s, irq6s, and irq7s) of the interrupt control register (icr) to select low level detection or falling edge detection for each pin. the priority level can be set from 0 to 15 for each pin using the interrupt priority registers a and b (ipra, iprb). when irq interrupts are set to low level detection, an interrupt request signal is sent to the intc during the period the irq pin is low level. interrupt request signals are not sent to the intc when the irq pin becomes high level. interrupt request levels can be confirmed by reading the irq flags (irq0f to irq3f, irq6f, and irq7f) of the irq status register (isr). when irq interrupts are set to falling edge detection, interrupt request signals are sent to the intc upon detecting a change on the irq pin from high to low level. irq interrupt request detection results are maintained until the interrupt request is accepted. confirmation that irq interrupt requests have been detected is possible by reading the irq flags (irq0f to irq3f, irq6f, and irq7f) of the irq status register (isr), and by writing a 0 after reading a 1, irq interrupt request detection results can be withdrawn. in irq interrupt exception processing, the interrupt mask bits (i3 to i0) of the status register (sr) are set to the priority level value of the accepted irq interrupt.
63 6.2.3 on-chip peripheral module interrupts on-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: ? multifunction timer pulse unit (mtu) ? compare match timer (cmt) ? serial communications interface (sci1) ? a/d converter (a/d) ? watchdog timer (wdt) ? 8-bit timer 2 (tim2) a different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers c to h (iprc to iprh). on-chip peripheral module interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.2.4 interrupt exception vectors and priority rankings table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. each interrupt source is allocated a different vector number and vector table address offset. vector table addresses are calculated from vector numbers and address offsets. in interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. see section 5 exception processing, table 5.4, calculating exception processing vector table addresses. irq interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers a to h (ipra to iprh). the ranking of interrupt sources for iprc to iprh, however, must be the order listed under priority order within ipr setting range in table 6.3 and cannot be changed. a power-on reset assigns priority level 0 to irq interrupts and on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 6.3.
64 table 6.3 interrupt exception processing vectors and priorities interrupt vector interrupt priority interrupt source vector no. vector table address offset priority (initial value) corre- sponding ipr (bits) within ipr setting range default priority nmi 11 h'0000002c to h'0000002f 16 high irq0 64 h'00000100 to h'00000103 0 to 15 (0) ipra (15 to 12) irq1 65 h'00000104 to h'00000107 0 to 15 (0) ipra (11 to 8) irq2 66 h'00000108 to h'0000010b 0 to 15 (0) ipra (7 to 4) irq3 67 h'0000010c to h'0000010f 0 to 15 (0) ipra (3 to 0) irq6 70 h'00000118 to h'0000011b 0 to 15 (0) iprb (7 to 4) irq7 71 h'0000011c to h'0000011f 0 to 15 (0) iprb (3 to 0) mtu0 tgi0a 88 h'00000160 to h'00000163 0 to 15 (0) iprd (15 to 12) high tgi0b 89 h'00000164 to h'00000167 0 to 15 (0) tgi0c 90 h'00000168 to h'0000016b 0 to 15 (0) tgi0d 91 h'0000016c to h'0000016f 0 to 15 (0) low tci0v 92 h'00000170 to h'00000173 0 to 15 (0) iprd (11 to 8) mtu1 tgi1a 96 h'00000180 to h'00000183 0 to 15 (0) iprd (7 to 4) high tgi1b 97 h'00000184 to h'00000187 0 to 15 (0) low tci1v 100 h'00000190 to h'00000193 0 to 15 (0) iprd (3 to 0) low
65 table 6.3 interrupt exception processing vectors and priorities (cont) interrupt vector interrupt priority interrupt source vector no. vector table address offset priority (initial value) corre- sponding ipr (bits) within ipr setting range default priority mtu2 tgi2a 104 h'000001a0 to h'000001a3 0 to 15 (0) ipre (15 to 12) high high tgi2b 105 h'000001a4 to h'000001a7 0 to 15 (0) low tci2v 108 h'000001b0 to h'000001b3 0 to 15 (0) ipre (11 to 8) sci1 eri1 132 h'00000210 to h'00000213 0 to 15 (0) iprf (3 to 0) high rxi1 133 h'00000214 to h'00000217 txi1 134 h'00000218 to h'0000021b tei1 135 h'0000021c to h'0000021f low a/d adi 138 h'00000228 to h'0000022b 0 to 15 (0) iprg (15 to 12) cmt0 cmi0 144 h'00000240 to h'00000243 0 to 15 (0) iprg (7 to 4) cmt1 cmi1 148 h'00000250 to h'00000253 0 to 15 (0) iprg (3 to 0) wdt iti 152 h'00000260 to h'00000263 0 to 15 (0) iprh (15 to 2) high tim2 cmi 153 h'00000264 to h'00000267 low low
66 6.3 description of registers 6.3.1 interrupt priority registers a to h (ipra to iprh) interrupt priority registers a to h (ipra to iprh) are 16-bit readable/writable registers that set priority levels from 0 to 15 for irq interrupts and on-chip peripheral module interrupts. correspondence between interrupt request sources and each of the ipra to iprh bits is shown in table 6.4. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 6.4 interrupt request sources and ipra to iprh bits register 15 to 12 11 to 8 7 to 4 3 to 0 interrupt priority register a irq0 irq1 irq2 irq3 interrupt priority register b reserved reserved irq6 irq7 interrupt priority register c reserved reserved reserved reserved interrupt priority register d mtu0 mtu0 mtu1 mtu1 interrupt priority register e mtu2 mttu2 reserved reserved interrupt priority register f reserved reserved reserved sci1 interrupt priority register g a/d reserved cmt0 cmt1 interrupt priority register h wdt, tim2 reserved reserved reserved as indicated in table 6.4, four irq pins or groups of 4 on-chip peripheral modules are allocated to each register. each of the corresponding interrupt priority ranks are established by setting a value from h'0 (0000) to h'f (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. interrupt priority rank becomes level 0 (lowest) by setting h'0, and level 15 (highest) by setting h'f. 8-bit timers 1 and 2 are set to the same priority rank.
67 ipra to iprh are initialized to h'0000 by a power-on reset. reserved bits are always read as 0. the write value should always be 0. it is not initialized in the standby mode. 6.3.2 interrupt control register (icr) the icr is a 16-bit register that sets the input signal detection mode of the external interrupt input pin nmi and irq0 to irq3 , irq6 , irq7 and indicates the input signal level to the nmi pin. a power-on reset initializes icr. it is not initialized in the standby mode. bit: 15 14 13 12 11 10 9 8 nmil nmie initial value: * 00 00 0 00 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 irq0s irq1s irq2s irq3s irq6s irq7s initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r r/w r/w note: * when nmi input is high: 1; when nmi input is low: 0 ? bit 15?mi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. bit 15: nmil description 0 nmi input level is low 1 nmi input level is high ? bits 14 to 9?eserved: these bits are always read as 0. the write value should always be 0. ? bit 8?mi edge select (nmie) bit 8: nmie description 0 interrupt request is detected on falling edge of nmi input (initial value) 1 interrupt request is detected on rising edge of nmi input
68 ? bits 7 to 4, 1, and 0?rq0 to irq3, irq6, and irq7 sense select (irq0s to irq3s, irq6s, irq7s): these bits set the irq0 to irq7 interrupt request detection mode. bits 7 to 4, 1, 0: irq0s to irq3s, irq6s, irq7s description 0 interrupt request is detected on low level of irq input (initial value) 1 interrupt request is detected on falling edge of irq input ? bits 3 and 2?eserved: these bits always read as 0. the write value should always be 0. 6.3.3 irq status register (isr) the isr is a 16-bit register that indicates the interrupt request status of the external interrupt input pins irq0 to irq3 , irq6 , and irq7 . when irq interrupts are set to edge detection, held interrupt requests can be withdrawn by writing a 0 to irqnf after reading an irqnf = 1. a power-on reset initializes isr. it is not initialized in the standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 irq0f irq1f irq2f irq3f irq6f irq7f initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r r/w r/w ? bits 15 to 8, 3, and 2?eserved: these bits are always read as 0. the write value should always be 0.
69 ? bits 7 to 4, 1, and 0?rq0 to irq3, irq6, and irq7 flags (irq0f to irq3f, irq6f, irq7f): these bits display the irq0 to irq3, irq6, irq7 interrupt request status. bits 7 to 4, 1, 0: irq0f to irq3f, irq6f, irq7f detection setting description 0 level detection no irqn interrupt request exists. clear conditions: when irqn input is high level edge detection no irqn interrupt request was detected. (initial value) clear conditions: 1. when a 0 is written after reading irqnf = 1 status 2. when irqn interrupt exception processing has been executed 1 level detection an irqn interrupt request exists. set conditions: when irqn input is low level edge detection an irqn interrupt request was detected. set conditions: when a falling edge occurs at an irqn input irq pin edge detection selection cpu interrupt request (irqn interrupt acceptance/irqnf = 0 write after irqnf = 1 read) s r resirqn q irqns (0: level, 1: edge) isr.irqnf level detection figure 6.2 external interrupt process
70 6.4 interrupt operation 6.4.1 interrupt sequence the sequence of interrupt operations is explained below. figure 6.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority level setting registers a to h (ipra to iprh). lower-priority interrupts are ignored*. if a number of interrupts with the same priority level occur, or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its ipr setting range (as indicated in table 6.3) is selected. 3. the interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (i3 to i0) in the cpu? status register (sr). if the request priority level is equal to or less than the level set in i3 to i0, the request is ignored. if the request priority level is higher than the level in bits i3 to i0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. 4. the interrupt controller detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. instead of executing the decoded instruction, the cpu starts interrupt exception processing (figure 6.5). 5. the status register (sr) and program counter (pc) are saved onto the stack. 6. the priority level of the accepted interrupt is written to bits i3 to i0 in sr. 7. the cpu reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. this jump is not a delay branch. note: an interrupt request for which edge detection has been set is held pending until it is accepted. however, an irq interrupt can be cleared by an irq status register (isr) access. for details see section 6.2.2, irq interrupts. pending edge-detected interrupts are cleared by a power-on reset.
71 no yes nmi? no yes level 15 interrupt? no yes i3 to i0 level 14? no yes level 14 interrupt? no yes yes i3 to i0 level 13? no yes level 1 interrupt? no yes i3 to i0 = level 0? no program execution state save sr to stack save pc to stack branches to exception service routine i3 to i0: interrupt mask bits of status register interrupt? copy accept-interrupt level to i3 to i0 reads exception vector table figure 6.3 interrupt sequence flowchart
72 6.4.2 stack after interrupt exception processing figure 6.4 shows the stack after interrupt exception processing. 32 bits 32 bits pc * 1 sr address 4n 8 4n 4 4n sp * 2 notes: 1. 2. pc: start address of the next instruction (return destination instruction) after the executing instruction always be certain that sp is a multiple of 4 figure 6.4 stack after interrupt exception processing 6.5 interrupt response time table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. figure 6.5 shows the pipeline when an irq interrupt is accepted.
73 table 6.5 interrupt response time number of states item nmi, peripheral module irq notes compare identified inter- rupt priority with sr mask level 23 wait for completion of sequence currently being executed by cpu x ( 0) the longest sequence is for interrupt or address-error exception processing (x = 4 + m1 + m2 + m3 + m4). if an interrupt-masking instruction follows, however, the time may be even longer. time from start of interrupt exception processing until fetch of first instruction of exception service routine starts 5 + m1 + m2 + m3 performs the pc and sr saves and vector address fetch. interrupt total 7 + m1 + m2 + m3 9 + m1 + m2 + m3 response minimum 10 12 20 mhz operation: 0.5 to 0.6 s time maximum 12 + 2 (m1 + m2 + m3) + m4 13 + 2 (m1 + m2 + m3) + m4 20 mhz operation: 0.95 to 1.0 s * note: * when m1 = m2 = m3 = m4 = 1 m1 to m4 are the number of states needed for the following memory accesses. m1: sr save (longword write) m2: pc save (longword write) m3: vector address read (longword read) m4: fetch first instruction of interrupt service routine
74 fde mee mme ee fd f 3 1 3 interrupt acceptance irq m1 m2 1 m3 1 5 + m1 + m2 + m3 instruction (instruction replaced by interrupt exception processing) overrun fetch interrupt service routine start instruction f: d: e: m: instruction fetch (instruction fetched from memory where program is stored). instruction decoding (fetched instruction is decoded). instruction execution (data operation and address calculation is performed according to the results of decoding). memory access (data in memory is accessed). figure 6.5 pipeline when an irq interrupt is accepted
75 section 7 bus state controller (bsc) 7.1 overview the bus state controller (bsc) divides up the address spaces and outputs control for various types of memory. this enables memories like sram and rom to be linked directly to the lsi without external circuitry. 7.1.1 features ? address space is divided into four spaces a maximum linear 2 mbytes for address space cs0 ? a maximum linear 4 mbytes for each of address spaces cs1 to cs3 ? 8-bit bus width ? wait states can be inserted by software for each space (0 to 3 waits) ? in external memory space access, wait states can be inserted by the wait pin ? outputs control signals for each space according to the type of memory connected ? ram interface ? on-chip ram access of 32 bits in 1 state
76 7.1.2 block diagram figure 7.1 shows the bsc block diagram. bus interface wcr1 bcr2 bcr1 internal bus wait control unit wait area control unit cs0 to cs3 rd memory control unit wrl module bus bsc wcr1: bcr1: bcr2: wait control register 1 bus control register 1 bus control register 2 figure 7.1 bsc block diagram
77 7.1.3 pin configuration table 7.1 shows the bus state controller pin configuration. table 7.1 pin configuration pin name i/o function a21 to a0 output address output d7 to d0 i/o 8-bit data bus cs0 to cs3 output chip select rd output strobe that indicates a read cycle for ordinary space/multiplex i/o wrl output strobe that indicates a write cycle wait input wait state request signal 7.1.4 register configuration the bus state controller has three registers. the functions of these registers include control of wait states and interfaces with memories such as rom and sram. the registers are summarized in table 7.2. both registers are 16 bits in size, and are initialized by a power-on reset. table 7.2 register configuration name abbr. r/w initial value address access size bus control register 1 bcr1 r/w h'200f h'ffff8620 8, 16 bus control register 2 bcr2 r/w h'ffff h'ffff8622 8, 16 wait state control register 1 wcr1 r/w h'ffff h'ffff8624 8, 16
78 7.1.5 address map figure 7.2 shows the address format used by this lsi. a31 a24 a23, a22 a21 output address: output from the address pins space selection: not output externally; used to select the type of space on-chip rom space or cs space when 00000000 (h'00) reserved (do not access) when 00000001 to 11111110 (h'01 to h'fe) on-chip peripheral module space or on-chip ram space when 11111111 (h'ff) cs space selection: decoded, outputs cs0 to cs3 when a31 to a24 = 00000000 a0 figure 7.2 address format this lsi uses 32-bit addresses: ? a31 to a24 are used to select the type of space and are not output externally. ? bits a23 and a22 are decoded and output as chip select signals ( cs0 to cs3 ) for the corresponding areas when bits a31 to a24 are 00000000. ? a21 to a0 are output externally. table 7.3 shows an address map.
79 table 7.3 address map address space memory size bus width h'00000000 to h'00027fff on-chip rom on-chip rom 160 kbytes 32 bits h'00028000 to h'001fffff reserved reserved h'00200000 to h'003fffff cs0 space ordinary space 2 mbytes 8 bits h'00400000 to h'007fffff cs1 space ordinary space 4 mbytes 8 bits h'00800000 to h'00bfffff cs2 space ordinary space 4 mbytes 8 bits h'00c00000 to h'00ffffff cs3 space ordinary space 4 mbytes 8 bits h'01000000 to h'ffff7fff reserved reserved h'ffff8000 to h'ffff87ff on-chip peripheral module on-chip peripheral module 2 kbytes 8/16 bits h'ffff8800 to h'ffffefff reserved reserved h'fffff000 to h'ffffffff on-chip ram on-chip ram 4 kbytes 32 bits note: do not access reserved spaces. operation cannot be guaranteed if they are accessed.
80 7.2 description of registers 7.2.1 bus control register 1 (bcr1) bit: 15 14 13 12 11 10 9 8 initial value: 0 0 1 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 a3sz a2sz a1sz a0sz initial value: 0 0 0 0 1 1 1 1 r/w: r r r r r/w r/w r/w r/w note: never write 1 to bits 4 to 7; doing so can result in unstable operation. bus control register 1 (bcr1) is a 16-bit readable/writeable register that specifies the bus size for each cs space. note that this chip requires that byte bus size (8 bits). initial settings should be written to bits 8 to 0 of bcr1 following a power-on reset, and the values should then be left unchanged. also, the cs spaces should not be accessed until initial setting of the registers has been completed. bcr1 is initialized to h'200f by a power-on reset. it is not initialized in the standby mode. ? bits 15, 14, and 12 to 4?eserved: these bits are always read as 0. the write value should always be 0. ? bit 13?eserved: this bit is always read as 1. the write value should always be 1. ? bit 3?s3 space size specification (a3sz): specifies the bus size for cs3. the SH7018 requires a byte bus size, so this bit must always be set to 0. bit 3: a3sz description 0 byte (8-bit) size 1 word (16-bit) size (initial value)
81 ? bit 2?s2 space size specification (a2sz): specifies the bus size for cs2. the SH7018 requires a byte bus size, so this bit must always be set to 0. bit 2: a2sz description 0 byte (8-bit) size 1 word (16-bit) size (initial value) ? bit 1?s1 space size specification (a1sz): specifies the bus size for cs1. the SH7018 requires a byte bus size, so this bit must always be set to 0. bit 1: a1sz description 0 byte (8-bit) size 1 word (16-bit) size (initial value) ? bit 0?s0 space size specification (a0sz): specifies the bus size for cs0. the SH7018 requires a byte bus size, so this bit must always be set to 0. bit 0: a0sz description 0 byte (8-bit) size 1 word (16-bit) size (initial value)
82 7.2.2 bus control register 2 (bcr2) bcr2 is a 16-bit read/write register that specifies the number of idle cycles and cs signal assert extension of each cs space. bcr2 is initialized by power-on resets to h'ffff. bit: 15 14 13 12 11 10 9 8 iw31 iw30 iw21 iw20 iw11 iw10 iw01 iw00 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 cw3 cw2 cw1 cw0 sw3 sw2 sw1 sw0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w ? bits 15 to 8?dles between cycles (iw31, iw30, iw21, iw20, iw11, iw10, iw01, iw00): these bits specify idle cycles inserted between consecutive accesses when the second one is to a different cs area after a read. idles are used to prevent data conflict between rom (and other memories, which are slow to turn the read data buffer off), fast memories, and i/o interfaces. even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. the idle cycles to be inserted comply with the area specification of the previous access . refer to section 7.4, waits between access cycles, for details. iw31 and iw30 specify the idle between cycles for the cs3 space; iw21 and iw20 specify the idle between cycles for the cs2 space; iw11 and iw10 specify the idle between cycles for the cs1 space, and iw01 and iw00 specify the idle between cycles for the cs0 space. bit 15 (iw31) bit 14 (iw30) description 0 0 no idle cycle after accessing cs3 space 1 inserts one idle cycle after accessing cs3 space 1 0 inserts two idle cycles after accessing cs3 space 1 inserts three idle cycles after accessing cs3 space ( initial value)
83 bit 13 (iw21) bit 12 (iw20) description 0 0 no idle cycle after accessing cs2 space 1 inserts one idle cycle after accessing cs2 space 1 0 inserts two idle cycles after accessing cs2 space 1 inserts three idle cycles after accessing cs2 space ( initial value) bit 11 (iw11) bit 10 (iw10) description 0 0 no idle cycle after accessing cs1 space 1 inserts one idle cycle after accessing cs1 space 1 0 inserts two idle cycles after accessing cs1 space 1 inserts three idle cycles after accessing cs1 space ( initial value) bit 9 (iw01) bit 8 (iw00) description 0 0 no idle cycle after accessing cs0 space 1 inserts one idle cycle after accessing cs0 space 1 0 inserts two idle cycles after accessing cs0 space 1 inserts three idle cycles after accessing cs0 space ( initial value) ? bits 7 to 4?dle specification for continuous access (cw3, cw2, cw1, cw0): the continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the csn signal when doing consecutive accesses of the same cs space. when a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by iw and cw. refer to section 7.4, waits between access cycles, for details. cw3 specifies the continuous access idles for the cs3 space; cw2 specifies the continuous access idles for the cs2 space; cw1 specifies the continuous access idles for the cs1 space and cw0 specifies the continuous access idles for the cs0 space.
84 bit 7 (cw3) description 0 no cs3 space continuous access idle cycles 1 one cs3 space continuous access idle cycle (initial value) bit 6 (cw2) description 0 no cs2 space continuous access idle cycles 1 one cs2 space continuous access idle cycle (initial value) bit 5 (cw1) description 0 no cs1 space continuous access idle cycles 1 one cs1 space continuous access idle cycle (initial value) bit 4 (cw0) description 0 no cs0 space continuous access idle cycles 1 one cs0 space continuous access idle cycle (initial value) ? bits 3 to 0 cs assert extension specification (sw3, sw2, sw1, sw0): the cs assert cycle extension specification is for making insertions to prevent extension of the rd signal or wrl signal assert period beyond the length of the csn signal assert period. extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending write data hold time. refer to section 7.3.3, cs assert period extension, for details. sw3 specifies the cs assert extension for cs3 space access; sw2 specifies the cs assert extension for cs2 space access; sw1 specifies the cs assert extension for cs1 space access and sw0 specifies the cs assert extension for cs0 space access. bit 3 (sw3) description 0 no cs3 space cs assert extension 1 cs3 space cs assert extension (initial value) bit 2 (sw2) description 0 no cs2 space cs assert extension 1 cs2 space cs assert extension (initial value)
85 bit 1 (sw1) description 0 no cs1 space cs assert extension 1 cs1 space cs assert extension (initial value) bit 0 (sw0) description 0 no cs0 space cs assert extension 1 cs0 space cs assert extension (initial value)
86 7.2.3 wait control register 1 (wcr1) wait control register 1 (wcr1) is a 16-bit read/write register that specifies the number of wait cycles (0 to 3) for each cs space. wcr1 is initialized to h'ffff by power-on resets. bit: 15 14 13 12 11 10 9 8 w31 w30 w21 w20 initial value: 1 1 1 1 1 1 1 1 r/w: r r r/w r/w r r r/w r/w bit: 7 6 5 4 3 2 1 0 w11 w10 w01 w00 initial value: 1 1 1 1 1 1 1 1 r/w: r r r/w r/w r r r/w r/w ? bits 15 and 14?eserved: these bits are always read as 1. the write value should always be 1. ? bits 13 and 12?s3 space wait specification (w31, w30): these bits specify the number of waits for cs3 space accesses. bit 13 (w31) bit 12 (w30) description 0 0 no wait (external wait input disabled) 1 1-wait external wait input enabled 1 0 2-wait external wait input enabled 1 3-wait external wait input enabled (initial value) ? bits 11 and 10?eserved: these bits are always read as 1. the write value should always be 1.
87 ? bits 9 and 8?s2 space wait specification (w21, w20): these bits specify the number of waits for cs2 space accesses. bit 9 (w21) bit 8 (w20) description 0 0 no wait (external wait input disabled) 1 1-wait external wait input enabled 1 0 2-wait external wait input enabled 1 3-wait external wait input enabled (initial value) ? bits 7 and 6?eserved. either 0 or 1 can be written. these bits read the written value. ? bits 5 and 4?s1 space wait specification (w11, w10): these bits specify the number of waits for cs1 space accesses. bit 5 (w11) bit 4 (w10) description 0 0 no wait (external wait input disabled) 1 1-wait external wait input enabled 1 0 2-wait external wait input enabled 1 3-wait external wait input enabled (initial value) ? bits 3 and 2?eserved. either 0 or 1 can be written. these bits read the written value. ? bits 1 and 0?s0 space wait specification (w01, w00): these bits specify the number of waits for cs0 space accesses. bit 1 (w01) bit 0 (w00) description 0 0 no wait (external wait input disabled) 1 1-wait external wait input enabled 1 0 2-wait external wait input enabled 1 3-wait external wait input enabled (initial value)
88 7.3 accessing ordinary space a strobe signal is output by ordinary space accesses to provide primarily for sram or rom direct connections. 7.3.1 basic timing figure 7.3 shows the basic timing of ordinary space accesses. ordinary access bus cycles are performed in 2 states. t 1 ck address csn rd read write data wrl data t 2 figure 7.3 basic timing of ordinary space access during a read, irrespective of operand size, all bits in the data bus width for the access space (address) are fetched by the lsi on rd , using the required byte locations. during a write, the following signals are associated with transfer of these actual byte locations: wrl (bits 7 to 0).
89 7.3.2 wait state control the number of wait states inserted into ordinary space access states can be controlled using the wcr settings. the specified number of t w cycles (0 to 3 waits) are inserted as software wait cycles with the timing shown in figure 7.4. t 1 t w ck read write address csn rd data wrl data t 2 figure 7.4 wait timing of ordinary space access (software wait only)
90 when the wait is specified by software using wcr, the wait input wait signal from outside is sampled. figure 7.5 shows the wait signal sampling. the wait signal is sampled at the clock rise one cycle before the clock rise when t w state shifts to t 2 state. t 1 t w ck read write address csn wait rd data wrl data t w t w 0 t 2 figure 7.5 wait state timing of ordinary space access (wait states from software wait 2 state + wait signal)
91 7.3.3 cs assert period extension idle cycles can be inserted to prevent extension of the rd signal or wrl signal assert period beyond the length of the csn signal assert period by setting the sw3 to sw0 bits of bcr2. this allows for flexible interfaces with external circuitry. the timing is shown in figure 7.6. t h and t f cycles are added respectively before and after the ordinary cycle. only csn is asserted in these cycles; rd and wrl signals are not. further, data is extended up to the t f cycle, which is effective for gate arrays and the like, which have slower write operations. t h t 1 ck read write address csn rd data wrl data t 2 t f figure 7.6 cs assert period extension function
92 7.4 waits between access cycles when a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. if there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. to enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the same cs space by negating the csn signal once. 7.4.1 prevention of data bus conflicts for the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the iw31 to iw00 bits of the bcr2 is inserted. when idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles is inserted. figure 7.7 shows an example of idles between cycles. in this example, 1 idle between csn space cycles has been specified, so when a csm space write immediately follows a csn space read cycle, 1 idle cycle is inserted. ck csn csm rd data csn space read csm space write idle cycle wrl address t 1 t 2 t 1 t 2 t idle figure 7.7 idle cycle insertion example
93 iw31 and iw30 specify the number of idle cycles required after a cs3 space read either to read other external spaces, or for this lsi, to do write accesses. in the same manner, iw21 and iw20 specify the number of idle cycles after a cs2 space read, iw11 and iw10, the number after a cs1 space read, and iw01 and iw00, the number after a cs0 space read. 0 to 3 cycles can be specified for cs space. 7.4.2 simplification of bus cycle start detection for consecutive accesses of the same cs space, waits are inserted so that the number of idle cycles designated by the cw3 to cw0 bits of the bcr2 occur. however, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the iw and cw bits. when idle cycles already exist between access cycles, waits are not inserted. figure 7.8 shows an example. a continuous access idle is specified for csn space, and csn space is consecutively write accessed. ck csn rd wrl data csn space access csn space access idle cycle address t 1 t 2 t 1 t 2 t idle figure 7.8 same space consecutive access idle cycle insertion example
94 7.5 memory connection examples SH7018 256k 8 bits rom ce oe csn rd axx d0 to d7 axx i/o0 to i/o7 figure 7.9 8-bit data bus width rom connection SH7018 128k 8 bits sram csn rd cs oe axx axx wrl we d0 to d7 i / o0 to i/o7 figure 7.10 8-bit data bus width sram connection
95 section 8 multifunction timer pulse unit (mtu) 8.1 overview the SH7018 has an on-chip 16-bit multifunction timer pulse unit (mtu) with three channels of 16-bit timers. 8.1.1 features ? can process a maximum of six different pulse outputs and inputs. ? has eight timer general registers (tgr), four for channel 0 and two each for channels 1 and 2, that can be set to function independently as output compare registers or (except for tgr0b and tgr0d of channel 0) as input capture registers. the channel 0 tgrc and tgrd registers can be used as buffer registers. ? can select six counter input clock sources for all channels ? all channels can be set for the following operating modes: ? compare match waveform output: 0 output/1 output/toggle output selectable. ? input capture function: selectable rising edge, falling edge, or both rising and falling edge detection. ? counter clearing function: counters can be cleared by a compare-match or input capture. ? synchronizing mode: two or more timer counters (tcnt) can be written to simultaneously. two or more timer counters can be simultaneously cleared by a compare- match or input capture. counter synchronization functions enable synchronized register input/output. ? pwm mode: pwm output can be provided with any duty cycle. when combined with the counter synchronizing function, enables up to four-phase* pwm output. note: * when channels 0 to 2 are set to pwm mode 1 ? channel 0 can be set for buffer operation ? input capture register double buffer configuration possible ? output compare register automatic re-write possible ? cascade connection operation ? can be operated as a 32-bit counter by using the channel 2 input clock for channel 1 overflow/underflow ? high speed access via internal 16-bit bus ? eleven interrupt sources ? channel 0 has two dual-function compare-match/input capture interrupts, two compare- match interrupts, and one overflow interrupt, which can be requested independently.
96 ? channels 1 and 2 have two compare-match/input capture interrupts, one overflow interrupt, and one underflow interrupt which can be requested independently. ? a/d converter conversion start trigger can be generated ? channel 0 to 2 compare-match/input capture signals can be used as a/d converter conversion start triggers.
97 table 8.1 summarizes the mtu functions. table 8.1 mtu functions item channel 0 channel 1 channel 2 counter clocks internal: / 1, /4, /16, /64, /256, /1024 six to each channel general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b general registers/buffer registers tgr0c tgr0d no no input/output pins tioc0a tioc0c tioc1a tioc1b tioc2a tioc2b counter clear function tgr compare-match or input capture tgr compare-match or input capture tgr compare-match or input capture compare 0 yes yes yes match 1 yes yes yes output toggle yes yes yes input capture function yes yes yes synchronization yes yes yes buffer operation yes no no pwm mode 1 yes yes yes pwm mode 2 yes yes yes a/d conversion start trigger tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture interrupt sources compare match/input capture 0a compare match/input capture 1a compare match/input capture 2a compare match 0b compare match/input capture 1b compare match/input capture 2b compare match/input capture 0c overflow overflow compare match 0d overflow
98 8.1.2 block diagram figure 8.1 is the block diagram of the mtu. [clock input] internal clock: /1 /4 /16 /64 /256 /1024 [interrupt request signal] channel 0: tgi0a tgi0b tgi0c tgi0d tci0v channel 1: tgi1a tgi1b tci1v channel 2: tgi2a tgi2b tci2v [i/o pins] channel 0: tioc0a tioc0c channel 1: tioc1a tioc1b channel 2: tioc2a tioc2b internal data bus a/d conversion start request signal bus i/f shared tsyr tstr control logic module data bus channel 0 to 2 control logic tcnt tgra tgrb tgrc tgrd tcnt tgra tgrb tcnt tgra tgrb channel 2 channel 1 channel 0 tcr tiorh tier tmdr tiorl tsr tcr tior tier tmdr tsr tcr tior tier tmdr tsr figure 8.1 mtu block diagram
99 8.1.3 pin configuration table 8.2 summarizes the mtu pins. table 8.2 pin configuration channel name pin name i/o function 0 input capture/output compare-match 0a tioc0a i/o tgr0a input capture input/output compare output/pwm output pin input capture/output compare-match 0c tioc0c i/o tgr0c input capture input/output compare output/pwm output pin 1 input capture/output compare-match 1a tioc1a i/o tgr1a input capture input/output compare output/pwm output pin input capture/output compare-match 1b tioc1b i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/output compare-match 2a tioc2a i/o tgr2a input capture input/output compare output/pwm output pin input capture/output compare-match 2b tioc2b i/o tgr2b input capture input/output compare output/pwm output pin note: the tioc pins output undefined values when they are set to input capture and timer output by the pin function controller (pfc).
100 8.1.4 register configuration table 8.3 summarizes the mtu register configuration. table 8.3 register configuration chan- nel name abbrevi- ation r/w initial value address access size (bits) * 1 shared timer start register tstr r/w h'00 h'ffff8240 8, 16 timer synchro register tsyr r/w h'00 h'ffff8241 0 timer control register 0 tcr0 r/w h'00 h'ffff8260 8, 16, 32 timer mode register 0 tmdr0 r/w h'c0 h'ffff8261 timer i/o control register 0h tior0h r/w h'00 h'ffff8262 timer i/o control register 0l tior0l r/w h'00 h'ffff8263 timer interrupt enable register 0 tier0 r/w h'40 h'ffff8264 timer status register 0 tsr0 r/(w) * 2 h'c0 h'ffff8265 timer counter 0 tcnt0 r/w h'0000 h'ffff8266 16, 32 general register 0a tgr0a r/w h'ffff h'ffff8268 general register 0b tgr0b r/w h'ffff h'ffff826a general register 0c tgr0c r/w h'ffff h'ffff826c general register 0d tgr0d r/w h'ffff h'ffff826e 1 timer control register 1 tcr1 r/w h'00 h'ffff8280 8, 16 timer mode register 1 tmdr1 r/w h'c0 h'ffff8281 timer i/o control register 1 tior1 r/w h'00 h'ffff8282 8 timer interrupt enable register 1 tier1 r/w h'40 h'ffff8284 8, 16, 32 timer status register 1 tsr1 r/(w) * 2 h'c0 h'ffff8285 timer counter 1 tcnt1 r/w h'0000 h'ffff8286 16, 32 general register 1a tgr1a r/w h'ffff h'ffff8288 general register 1b tgr1b r/w h'ffff h'ffff828a
101 table 8.3 register configuration (cont) chan- nel name abbrevi- ation r/w initial value address access size (bits) * 1 2 timer control register 2 tcr2 r/w h'00 h'ffff82a0 8, 16 timer mode register 2 tmdr2 r/w h'c0 h'ffff82a1 timer i/o control register 2 tior2 r/w h'00 h'ffff82a2 8 timer interrupt enable register 2 tier2 r/w h'40 h'ffff82a4 8, 16, 32 timer status register 2 tsr2 r/(w) * 2 h'c0 h'ffff82a5 timer counter 2 tcnt2 r/w h'0000 h'ffff82a6 16, 32 general register 2a tgr2a r/w h'ffff h'ffff82a8 general register 2b tgr2b r/w h'ffff h'ffff82aa notes: do not access empty addresses. 1. 16-bit registers (tcnt, tgr) cannot be read or written in 8-bit units. 2. write 0 to clear flags. 8.2 mtu register descriptions 8.2.1 timer control register (tcr) the tcr is an 8-bit read/write register for controlling the tcnt counter for each channel. the mtu has three tcr registers, one for each of the channels 0 to 2. tcr is initialized to h'00 by a power-on reset or the standby mode. channel 0: tcr0 bit: 7 6 5 4 3 2 1 0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w channels 1 and 2: tcr1, tcr2 bit: 7 6 5 4 3 2 1 0 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w
102 ? bits 7 to 5?ounter clear 2, 1, and 0 (cclr2, cclr1, cclr0): select the counter clear source for the tcnt counter. channel 0: bit 7: cclr2 bit 6: cclr1 bit 5: cclr0 description 0 0 0 tcnt clear disabled (initial value) 1 tcnt is cleared by tgra compare-match or input capture 1 0 tcnt is cleared by tgrb compare-match 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync * 1 1 0 0 tcnt clear disabled 1 tcnt is cleared by tgrc compare-match or input capture * 2 1 0 tcnt is cleared by tgrd compare-match * 2 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync * 1 notes: 1. setting the sync bit of the tsyr to 1 sets the synchronization. 2. when tgrc or tgrd are functioning as buffer registers, tcnt is not cleared because the buffer registers have priority and compare-match/input captures do not occur. channels 1 and 2: bit 7: reserved * 1 bit 6: cclr1 bit 5: cclr0 description 0 0 0 tcnt clear disabled (initial value) 1 tcnt is cleared by tgra compare-match or input capture 1 0 tcnt is cleared by tgrb compare-match or input capture 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync * 2 notes: 1. the bit 7 of channels 1 and 2 is reserved. this bit is always read as 0. the write value should always be 0. 2. setting the sync bit of the tsyr to 1 sets the synchronization. ? bits 4 and 3?lock edge 1 and 0 (ckeg1, ckeg0): ckeg1 and ckeg0 select the input clock edges. when counting is done on both edges of the internal clock the input clock frequency becomes 1/2 (example: both edges of /4 = rising edge of /2 ).
103 bit 4: ckeg1 bit 3: ckeg0 description 0 0 count on rising edges (initial value) 1 count on falling edges 1 x count on both rising and falling edges notes: 1. x: 0 or 1, don t care. 2. internal clock edge selection is effective when the input clock is /4 or slower. these settings are ignored when /1, or the overflow of another channel is selected for the input clock. ? bits 2 to 0?imer prescaler 2 to 0 (tpsc2 to tpsc0): tpsc2 to tpsc0 select the counter clock source for the tcnt. an independent clock source can be selected for each channel. table 8.4 shows the possible settings for each channel. table 8.4 mtu clock sources internal clock other channel channel /1 /4 /16 /64 /256 /1024 overflow 0 oooox x x 1 ooooox o 2 oooox ox note: symbols: o: setting possible x: setting not possible channel 0: bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count with /1 (initial value) 1 internal clock: count with /4 1 0 internal clock: count with /16 1 internal clock: count with /64 1 0 0 reserved (do not set) 1 reserved (do not set) 1 0 reserved (do not set) 1 reserved (do not set)
104 channel 1: bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count with /1 (initial value) 1 internal clock: count with /4 1 0 internal clock: count with /16 1 internal clock: count with /64 1 0 0 reserved (do not set) 1 reserved (do not set) 1 0 internal clock: count with /256 1 count with the tcnt2 overflow channel 2: bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count with /1 (initial value) 1 internal clock: count with /4 1 0 internal clock: count with /16 1 internal clock: count with /64 1 0 0 reserved (do not set) 1 reserved (do not set) 1 0 reserved (do not set) 1 internal clock: count with /1024
105 8.2.2 timer mode register (tmdr) the tmdr is an 8-bit read/write register that sets the operating mode for each channel. the mtu has three tmdr registers, one for each channel. tmdr is initialized to h'c0 by a power-on reset. channel 0: tmdr0 bit: 7 6 5 4 3 2 1 0 bfb bfa md3 md2 md1 md0 initial value: 1 1 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w channels 1 and 2: tmdr1, tmdr2 bit: 7 6 5 4 3 2 1 0 md3 md2 md1 md0 initial value: 1 1 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w ? bits 7 and 6?eserved: these bits are always read as 1. the write value should always be 1. ? bit 5?uffer operation b (bfb): designates whether to use the tgrb register for normal operation, or buffer operation in combination with the tgrd register. when using tgrd as a buffer register, no tgrd register input capture/output compares are generated. this bit is reserved in channels 1 and 2, which have no tgrd registers. it is always read as 0. the write value should always be 0. bit 5: bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd buffer operation ? bit 4?uffer operation a (bfa): designates whether to use the tgra register for normal operation, or buffer operation in combination with the tgrc register. when using tgrc as a buffer register, no tgrc register input capture/output compares are generated. this bit is reserved in channels 1 and 2, which have no tgrc registers. it is always read as 0. the write value should always be 0. bit 4: bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc buffer operation
106 ? bits 3 to 0?odes 3 to 0 (md3 to md0): these bits set the timer operation mode. bit 3: md3 bit 2: md2 bit 1: md1 bit 0: md0 description 0000 normal operation (initial value) 1 reserved (do not set) 1 0 pwm mode 1 1 pwm mode 2 01 ** reserved (do not set) 1 *** reserved (do not set) * : don t care 8.2.3 timer i/o control register (tior) the tior is a register that controls the tgr. the mtu has four tior registers, two for channel 0, and one each for channels 1 and 2. tior is initialized to h'00 by a power-on reset. channel 0: tior0h bit: 7 6 5 4 3 2 1 0 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w channels 1 and 2: tior1, tior2 bit: 7 6 5 4 3 2 1 0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 7 to 4?/o control b3 to b0 (iob3 to iob0): these bits set the tgrb register function. bit 7 of tior0h is reserved bit. it is always read as 0. the write value should always be 0. bits 3 to 0?/o control a3 to a0 (ioa3 to ioa0): these bits set the tgra register function.
107 channel 0: tior0l bit: 7 6 5 4 3 2 1 0 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w note: when the tgrc or tgrd registers are set for buffer operation, these settings become ineffective and the operation is as a buffer register. ? bit 7?eserved. this bit is always read as 0. the write value should always be 0. ? bits 6 to 4?/o control d2 to d0 (iod2 to iod0): these bits set the tgrd register function. ? bits 3 to 0?/o control c3 to c0 (ioc3 to ioc0): these bits set the tgrc register function. channel 0 (tior0h register): bit 6: iob2 bit 5: iob1 bit 4: iob0 description 0 0 0 tgr0b is an output output disabled (initial value) 1 compare register initial output 0 on compare-match 10 output output 1 on compare-match 1 is 0 toggle output on compare-match 1 0 0 output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match
108 bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 0 0 0 0 tgr0a output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr0a capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc0a pin 10 0 register capture input capture 1 input source on tcnt1 10 is channel 1/ count up/count down 1 count clock
109 channel 0 (tior0l register): bit 6: iod2 bit 5: iod1 bit 4: iod0 description 0 0 0 tgr0d is an output output disabled (initial value) 1 compare register initial output 0 on compare-match 10 output output 1 on compare-match 1 is 0 toggle output on compare-match 1 0 0 output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match bit 3: ioc3 bit 2: ioc2 bit 1: ioc1 bit 0: ioc0 description 0 0 0 0 tgr0c output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr0c capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc0c pin 10 0 register capture input capture 1 input source on tcnt1 10 is channel 1/ count up/count down 1 count clock note: when the bfa bit of tmdr0 is set to 1 and tgr0c is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur.
110 channel 1 (tior1 register): bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 0 0 0 0 tgr1b output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr1b capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc1b pin 10 0 register capture input input capture 1 source tgr0c on channel tgr0c 10 compare/match compare-match/input 1 input capture capture generation
111 bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 0 0 0 0 tgr1a output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr1a capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc1a pin 10 0 register capture input input capture 1 source is tgr0a on channel 0/tgr0a 10 compare- match/input compare-match/input capture generation 1 capture
112 channel 2 (tior2 register): bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 0 0 0 0 tgr2b output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr2b capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc2b pin 10 0 register input capture on rising edge 1 input capture on falling edge 1 0 input capture on both edges 1
113 bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 0 0 0 0 tgr2a output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr2a capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc2a pin 10 0 register input capture on rising edge 1 input capture on falling edge 1 0 input capture on both edges 1
114 8.2.4 timer interrupt enable register (tier) the tier is an 8-bit register that controls the enable/disable of interrupt requests for each channel. the mtu has three tier registers, one each for channel. tier is initialized to h'40 by a power- on reset. channel 0: tier0 bit: 7 6 5 4 3 2 1 0 ttge tciev tgied tgiec tgieb tgiea initial value: 0 1 0 0 0 0 0 0 r/w: r/w r r r/w r/w r/w r/w r/w channels 1 and 2: tier1, tier2 bit: 7 6 5 4 3 2 1 0 ttge tciev tgieb tgiea initial value: 0 1 0 0 0 0 0 0 r/w: r/w r r r/w r r r/w r/w ? bit 7?/d conversion start request enable (ttge): enables or disables generation of an a/d conversion start request by a tgra register input capture/compare-match. bit 7: ttge description 0 disable a/d conversion start requests generation (initial value) 1 enable a/d conversion start request generation ? bit 6?eserved: this bit is always read as 1. the write value should always be 1. ? bit 5?eserved. this bit is always read as 0. the write value should always be 0. ? bit 4?verflow interrupt enable (tciev): enables or disables interrupt requests when the overflow flag tcfv of the timer status register (tsr) is set to 1. bit 4: tciev description 0 disable tcfv interrupt requests (tciv) (initial value) 1 enable tcfv interrupt requests (tciv)
115 ? bit 3?gr interrupt enable d (tgied): enables or disables interrupt tgfd requests when the tgfd bit of the channel 0 of the tsr register is set to 0. this bit is reserved for channels 1 and 2. it is always read as 0. the write value should always be 0. bit 3: tgied description 0 disable interrupt requests (tgid) due to the tgfd bit (initial value) 1 enable interrupt requests (tgid) due to the tgfd bit ? bit 2?gr interrupt enable c (tgiec): enables or disables tgfc interrupt requests when the tgfc bit of the channel 0 of the tsr register is set to 1. this bit is reserved for channels 1 and 2. it is always read as 0. the write value should always be 0. bit 2: tgiec description 0 disable interrupt requests (tgic) due to the tgfc bit (initial value) 1 enable interrupt requests (tgic) due to the tgfc bit ? bit 1?gr interrupt enable b (tgieb): enables or disables tgfb interrupt requests when the tgfb bit of the tsr register is set to 1. bit 1: tgieb description 0 disable interrupt requests (tgib) due to the tgfb bit (initial value) 1 enable interrupt requests (tgib) due to the tgfb bit ? bit 0?gr interrupt enable a (tgiea): enables or disables tgfa interrupt requests when the tgfa bit of the tsr register is set to 1. bit 0: tgiea description 0 disable interrupt requests (tgia) due to the tgfa bit (initial value) 1 enable interrupt requests (tgia) due to the tgfa bit
116 8.2.5 timer status register (tsr) the timer status register (tsr) is an 8-bit register that indicates the status of each channel. the mtu has three tsr registers, one each for channel. tsr is initialized to h'c0 by a power-on reset. channel 0: tsr0 bit: 7 6 5 4 3 2 1 0 tcfv tgfd tgfc tgfb tgfa initial value: 1 1 0 0 0 0 0 0 r/w: r r r r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 writes to clear the flags are possible. channels 1 and 2: tsr1, tsr2 bit: 7 6 5 4 3 2 1 0 tcfv tgfb tgfa initial value: 1 1 0 0 0 0 0 0 r/w: r r r r/(w) * r r r/(w) * r/(w) * note: * only 0 writes to clear the flags are possible. ? bits 7 and 6?eserved: these bits are always read as 1. the write value should always be 1. ? bit 5?eserved: this bit is always read as 0. the write value should always be 0. ? bit 4?verflow flag (tcfv): this status flag indicates the occurrence of a tcnt counter overflow. bit 4: tcfv description 0 clear condition: with tcfv =1, a 0 write to tcfv after reading it (initial value) 1 set condition: when the tcnt value overflows (h'ffff h'0000)
117 ? bit 3?utput compare flag d (tgfd): this status flag indicates the occurrence of a channel 0 tgrd register compare-match. this bit is reserved in channels 1 and 2. it is always read as 0. the write value should always be 0. bit 3: tgfd description 0 clear condition: with tgfd = 1, a 0 write to tgfd following a read (initial value) 1 set condition: when tcnt = tgrd while tgrd is functioning as an output compare register ? bit 2?nput capture/output compare flag c (tgfc): this status flag indicates the occurrence of a channel 0 tgrc register input capture or compare-match. this bit is reserved for channels 1 and 2. it is always read as 0. the write value should always be 0. bit 2: tgfc description 0 clear condition: with tgfc = 1, a 0 write to tgfc following a read (initial value) 1 set conditions: ? when tgrc is functioning as an output compare register (tcnt = tgrc) ? when tgrc is functioning as input capture (the tcnt value is sent to tgrc by the input capture signal) ? bit 1?utput compare flag b (tgfb): this status flag indicates the occurrence of a tgrb register compare-match. bit 1: tgfb description 0 clear condition: with tgfb = 1, a 0 write to tgfb following a read (initial value) 1 set conditions: when tgrb is functioning as an output compare register (tcnt = tgrb)
118 ? bit 0?nput capture/output compare flag a (tgfa): this status flag indicates the occurrence of a tgra register input capture or compare-match. bit 0: tgfa description 0 clear condition: with tgfa = 1, a 0 write to tgfa following a read (initial value) 1 set conditions: ? when tgra is functioning as an output compare register (tcnt = tgra) ? when tgra is functioning as input capture (the tcnt value is sent to tgra by the input capture signal) 8.2.6 timer counters (tcnt) the timer counters (tcnt) are 16-bit counters, with one for each channel, for a total of three. the tcnt are initialized to h'0000 by a power-on reset. accessing the tcnt counters in 8-bit units is prohibited. always access in 16-bit units. channel 0: tcnt0 channel 1: tcnt1 channel 2: tcnt2 bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
119 8.2.7 timer general register (tgr) each timer general register (tgr) is a 16-bit register that can function as either an output compare register or an input capture register. there are a total of eight tgr, four each for channels 0 and two each for channels 1 and 2. the tgrc and tgrd of channels 0 can be set to operate as buffer registers. the tgr register and buffer register combinations are tgra with tgrc, and tgrb with tgrd. the tgrs are initialized to h'ffff by a power-on reset. accessing of the tgrs in 8-bit units is disabled; they may only be accessed in 16-bit units. bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 8.2.8 timer start register (tstr) the timer start register (tstr) is an 8-bit read/write register that starts and stops the timer counters (tcnt) of channels 0 to 2. tstr is initialized to h'00 upon power-on reset. bit: 7 6 5 4 3 2 1 0 cst2 cst1 cst0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w ? bits 7 to 3?eserved: these bits are always read as 0. the write value should always be 0. ? bits 2 to 0?ounter start 2 to 0 (cst2 to cst0): select starting and stopping of the timer counters (tcnt). the corresponding between bits and channels is as follows: cst2: channel 2 (tcnt2) cst1: channel 1 (tcnt1) cst0: channel 0 (tcnt0)
120 bit n: cstn description 0 tcntn count is halted (initial value) 1 tcntn counts note: n = 2 to 0. if 0 is written to a cst bit during operation with the tioc pin in the output state, the counter stops, but the tioc pin output compare output level is maintained. if a write is performed on the tior register while a cst bit is 0, the pin output level is updated to the set initial output value. 8.2.9 timer synchro register (tsyr) the timer synchro register (tsyr) is an 8-bit read/write register that selects independent or synchronous tcnt counter operation for channels 0 to 2. channels for which 1 is set in the corresponding bit will be synchronized. tsyr is initialized to h'00 upon power-on reset. bit: 7 6 5 4 3 2 1 0 sync2 sync1 sync0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w ? bits 7 to 3?eserved: these bits are always read as 0. the write value should always be 0. ? bits 2 to 0?imer synchronization 2 to 0 (sync2 to sync0): selects operation independent of, or synchronized to, other channels. synchronous operation allows synchronous clears due to multiple tcnt synchronous presets and other channel counter clears. a minimum of two channels must have sync bits set to 1 for synchronous operation. for synchronization clearing, it is necessary to set the tcnt counter clear sources (the cclr2 to cclr0 bits of the tcr register), in addition to the sync bit. the counter start to channel and bit-to-channel correspondence are indicated in the tables below. sync2: channel 2 (tcnt2) sync1: channel 1 (tcnt1) sync0: channel 0 (tcnt0)
121 bit n: syncn description 0 timer counter (tcntn) independent operation (initial value) (tcntn preset/clear unrelated to other channels) 1 timer counter synchronous operation * 1 tcntn synchronous preset/ synchronous clear * 2 possible note: 1. minimum of two channel sync bits must be set to 1 for synchronous operation. 2. tcnt counter clear sources (cclr2 to cclr0 bits of the tcr register) must be set in addition to the sync bit in order to have clear synchronization. n = 2 to 0. 8.3 bus master interface 8.3.1 16-bit registers the timer counters (tcnt) and general registers (tgr) are 16-bit registers. a 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. always access in 16-bit units. figure 8.2 shows an example of 16-bit register access operation. tcnth bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus tcntl figure 8.2 16-bit register access operation (bus master ? ? ? ? tcnt (16 bits)) 8.3.2 8-bit registers all registers other than the tcnt and general registers (tgr) are 8-bit registers. these are connected to the cpu by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both possible (figure 8.3 to figure 8.5).
122 tcr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 8.3 8-bit register access operation (bus master ? ? ? ? tcr (upper 8 bits)) tmdr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 8.4 8-bit register access operation (bus master ? ? ? ? tmdr (lower 8 bits)) tcr tmdr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 8.5 8-bit register access operation (bus master ? ? ? ? tcr, tmdr (16 bits))
123 8.4 operation 8.4.1 overview the operation modes are described below. ordinary operation: each channel has a timer counter (tcnt) and general register (tgr). the tcnt is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. general registers (tgr) can be used as output compare registers or input capture registers. synchronized operation: the tcnt of a channel set for synchronized operation does a synchronized preset. when any tcnt of a channel operating in the synchronized mode is rewritten, the tcnts of other channels are simultaneously rewritten as well. the timer synchronization bits of the tsyr registers of multiple channels set for synchronous operation can be set to clear the tcnts simultaneously. buffer operation: when tgr is an output compare register, the buffer register value of the corresponding channel is transferred to the tgr when a compare-match occurs. when tgr is an input capture register, the tcnt counter value is transferred to the tgr when an input capture occur simultaneously the value previously stored in the tgr is transferred to the buffer register. cascade connection operation : the channel 1 and channel 2 counters (tcnt1 and tcnt2) can be connected together to operate as a 32-bit counter. pwm mode: in pwm mode, a pwm waveform is output. the output level can be set by the tior register. each tgr can be set for pwm waveform output with a duty cycle between 0% and 100%. 8.4.2 basic functions always select mtu external pin set function using the pin function controller (pfc). counter operation: when a start bit (cst0 to cst2) in the timer start register (tstr) is set to 1, the corresponding timer counter (tcnt) starts counting. there are two counting modes: a free- running mode and a periodic mode. to select the counting operation (figure 8.6): 1. set bits tpsc2 to tpsc0 in the tcr to select the counter clock. at the same time, set bits ckeg1 and ckeg0 in the tcr to select the desired edge of the input clock. 2. to operate as a periodic counter, set the cclr2 to cclr0 bits in the tcr to select tgr as a clearing source for the tcnt.
124 3. set the tgr selected in step 2 as an output compare register using the timer i/o control register (tior). 4. write the desired cycle value in the tgr selected in step 2. 5. set the cst bit in the tstr to 1 to start counting. counting mode selection select counter clock periodic counter select counter clear source select output compare register set period start counting start counting free-running counter periodic counter free-running counter (5) (5) (4) (3) (2) (1) figure 8.6 procedure for selecting the counting operation free-running counter operation example: a reset of the mtu timer counters (tcnt) leaves them all in the free-running mode. when a bit in the tstr is set to 1, the corresponding timer counter operates as a free-running counter and begins to increment. when the count overflows from h'ffff to h'0000, the tcfv bit in the timer status register (tsr) is set to 1. if the tciev bit in the timer? corresponding timer interrupt enable register (tier) is set to 1, the mtu will make an interrupt request to the interrupt controller. after the tcnt overflows, counting continues from h'0000. figure 8.7 shows an example of free-running counter operation.
125 cst bit tcnt value time h'ffff h'0000 tcfv figure 8.7 free-running counter operation periodic counter operation example: periodic counter operation is obtained for a given channel? tcnt by selecting compare-match as a tcnt clear source. set the tgr register for period setting to output compare register and select counter clear upon compare-match using the cclr2 to cclr0 bits of the timer control register (tcr). after these settings, the tcnt begins incrementing as a periodic counter when the corresponding bit of tstr is set to 1. when the count matches the tgr register value, the tgf bit in the tsr is set to 1 and the counter is cleared to h'0000. if the tgie bit of the corresponding tier is set to 1 at this point, the mtu will make an interrupt request to the interrupt controller. after the compare-match, tcnt continues counting from h'0000. figure 8.8 shows an example of periodic counting. cst bit tcnt value time counter cleared by tgr compare match tgr h'0000 tgf flag cleared by software activation figure 8.8 periodic counter operation
126 compare-match waveform output function: the mtu can output 0 level, 1 level, or toggle output from the corresponding output pins upon compare-matches. procedure for selecting the compare-match waveform output operation (figure 8.9): 1. set the tior to select 0 output or 1 output for the initial value, and 0 output, 1 output, or toggle output for compare-match output. the tioc pin will output the set initial value until the first compare-match occurs. 2. set a value in the tgr to select the compare-match timing. 3. set the cst bit in the tstr to 1 to start counting. output selection select waveform output mode select output timing start counting (1) (2) (3) figure 8.9 procedure for selecting compare match waveform output operation waveform output operation (0 output/1 output): figure 8.10 shows 0 output/1 output. in the example, tcnt is a free-running counter, 1 is output upon compare-match a and 0 is output upon compare-match b. when the pin level matches the set level, the pin level does not change.
127 h'ffff h'0000 tioca tcnt value time tgra tgrb tiocb does not change does not change 1 output does not change does not change 0 output figure 8.10 example of 0 output/1 output waveform output operation (toggle output): figure 8.11 shows the toggle output. in the example, the tcnt operates as a periodic counter cleared by compare-match b, with toggle output at both compare-match a and compare-match b. h'ffff h'0000 tiocb tcnt value counter cleared by tgrb compare match time tgrb tgra tioca toggle output toggle output figure 8.11 example of toggle output input capture function: in the input capture mode, the tcnt value is transferred into the tgr register when the input edge is detected at the input capture/output compare pin (tioc). detection can take place on the rising edge, falling edge, or both edges. channels 0 and 1 can use other channel counter input clocks or compare-match signals as input capture sources.
128 the procedure for selecting the input capture operation (figure 8.12) is: 1. set the tior to select the input capture function of the tgr, then select the input capture source, and rising edge, falling edge, or both edges as the input edge. 2. set the cst bit in the tstr to 1 to start the tcnt counting. input selection select input-capture input start counting input capture operation (1) (2) figure 8.12 procedure for selecting input capture operation input capture operation: figure 8.13 shows input capture. the falling edge of tiocb and both edges of tioca are selected as input capture input edges. in the example, tcnt is set to clear at the input capture of the tgrb register. counter cleared by tiocb input (falling edge) tcnt value h'0180 h'0160 h'0005 h'0010 h'0000 tiocb tioca tgra tgrb h'0005 h'0160 h'0010 h'0180 time figure 8.13 input capture operation
129 8.4.3 synchronous operation there are two kinds of synchronous operation, synchronized preset and synchronized clear. the synchronized preset operation allows multiple timer counters (tcnt) to be rewritten simultaneously, while the synchronized clear operation allows multiple tcnt counters to be cleared simultaneously using timer control register (tcr) settings. the synchronizing mode can increase the number of tgr registers for a single time base. all five channels can be set for synchronous operation. procedure for selecting the synchronizing mode (figure 8.14): 1. set 1 in the sync bit of the timer synchro register (tsyr) to use the corresponding channel in the synchronizing mode. 2. when a value is written in the tcnt in any of the synchronized channels, the same value is simultaneously written in the tcnt in the other channels. 3. set the counter to clear with output compare/input capture using bits cclr2 to cclr0 in the tcr. 4. set the counter clear source to synchronized clear using the cclr2 to cclr0 bits of the tcr. 5. set the cst bits for the corresponding channels in the tstr to 1 to start counting in the tcnt. select counter clear source channel that generated clear source? no yes select synchronizing mode set synchronizing mode synchronized preset set tcnt start counting set counter synchronous clear start counting counter clear synchronized clear synchronized preset synchronized clear (1) (2) (3) (5) (4) (5) figure 8.14 procedure for selecting synchronizing operation
130 synchronized operation: figure 8.15 shows an example of synchronized operation. channels 0, 1, and 2 are set to synchronized operation and pwm mode 1. channel 0 is set for a counter clear upon compare-match with tgr0b. channels 1 and 2 are set for synchronous counter clears by synchronous presets and tgr0b register compare-matches. accordingly, a three-phase pwm waveform with the data set in the tgr0b register as its pwm period is output from the tioc0a, tioc1a, and tioc2a pins. see section 8.4.6, pwm mode, for details on the pwm mode. tcnt0 tcnt2 values time tioc0a synchronized clear on tgr0b compare match tgr0b tgr1b tgr0a tgr2b tgr1a tgr2a h'0000 tioc1a tioc2a figure 8.15 synchronized operation example
131 8.4.4 buffer operation buffer operation is a function of channel 0. tgrc and tgrd can be used as buffer registers. table 8.5 shows the register combinations for buffer operation. table 8.5 register combinations channel general register buffer register 0 tgr0a tgr0c tgr0b tgr0d the buffer operation differs, depending on whether the tgr has been set as an input capture register or an output compare register. when tgr is an output compare register: when a compare-match occurs, the corresponding channel buffer register value is transferred to the general register. figure 8.16 shows an example. compare match signal buffer register tcnt comparator general register figure 8.16 compare match buffer operation when tgr is an input capture register: when an input capture occurs, the timer counter (tcnt) value is transferred to the general register (tgr), and the value that had been held up to that time in the tgr is transferred to the buffer register (figure 8.17). input capture signal tcnt buffer register general register figure 8.17 input capture buffer operation
132 procedure for setting buffer mode (figure 8.18): 1. use the timer i/o control register (tior) to set the tgr as either an input capture or output compare register. 2. use the timer mode register (tmdr) bfa, and bfb bits to set the tgr for buffer mode. 3. set the cst bit in the tstr to 1 to start the count operation. (1) (2) (3) select tgr function buffer mode select buffer mode start counting buffer mode figure 8.18 buffer operation setting procedure buffer operation examples?hen tgr is an output compare register: figure 8.19 shows an example of channel 0 set to pwm mode 1, and the tgra and tgrc registers set for buffer operation. the tcnt counter is cleared by a compare-match b, and the output is a 1 upon compare-match a and 0 output upon compare-match b. because buffer mode is selected, a compare-match a changes the output, and the buffer register tgrc value is simultaneously transferred to the general register tgra. this operation is repeated with each occurrence of a compare-match a. see section 8.4.6, pwm mode, for details on the pwm mode.
133 tgr0b tgr0a h'0000 tgr0c tgr0a tioc0a h'0450 h'0520 h'0200 h'0450 h'0520 h'0200 tcnt value time transfer h'0450 h'0200 figure 8.19 buffer operation example (output compare register) buffer operation examples?hen tgr is an input capture register: figure 8.20 shows an example of tgra set as an input capture register with the tgra and tgrb registers set for buffer operation. the tcnt counter is cleared by a tgra register input capture, and the tioca pin input capture input edge is selected as both rising and falling edge. because buffer mode is selected, an input capture a causes the tcnt counter value to be stored in the tgra register, and the value that was stored in the tgra up until that time is simultaneously transferred to the tgrc register. h'0f07 h'09fb h'0532 h'0000 tgra tgrc tioc0a h'0532 h'09fb h'0f07 tcnt value time h'0f07 h'0532 figure 8.20 buffer operation example (input capture register)
134 8.4.5 cascade connection mode cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. this function operates by using the tpsc2 to tpsc0 bits of the tcr register to set the channel 1 counter clock to count by tcnt2 counter overflow. table 8.6 shows the cascade connection combinations. table 8.6 cascade connection combinations combination upper 16 bits lower 16 bits channel 1, channel 2 tcnt1 tcnt2 procedure for setting cascade connection mode (figure 8.21): 1. set the tpsc2 to tpsc 0 bits of the channel 1 timer control register (tcr) to b'111 to select ?ount by tcnt2 overflow. 2. set the cst bits corresponding to the upper and lower 16 bits in the tstr to 1 to start the count operation. cascade connection operation select cascade connection start counting cascade connection operation (1) (2) figure 8.21 procedure for selecting cascade connection mode cascade connection mode examples?nput capture: figure 8.22 shows an example of operation when the tcnt1 counter is set to count on tcnt2 overflow, the tgr1a and tgr2a registers are set as input capture registers, and the tioc pin rising edge is selected. through simultaneous input of the rising edge to the tioc1a and tioc2a pins, 32-bit data is transferred, with the upper 16 bits to the tgr1a register and the lower 16 bits to the tgr2a register.
135 tcnt1 clock tcnt2 clock tioc1a, tioc2a tcnt1 h'03a1 h'ffff h'0000 h'0001 h'03a2 tcnt2 tgr1a h'03a2 tgr2a h'0000 figure 8.22 cascade connection operation example (input capture) 8.4.6 pwm mode pwm mode outputs the various pwm waveforms from output pins. output levels of 0 output, 1 output, or toggle output can be selected as the output level for the compare-match of each tgr. a period can be set for a register by using the tgr compare-match as a counter clear source. all five channels can be independently set to pwm mode. synchronous operation is also possible. there are two pwm modes: ? pwm mode 1 generates pwm output using the tgra and tgrb registers, and tgrc and tgrd registers as pairs. the initial output values are those established in the tgra and tgrc registers. when the values set in tgr registers being used as a pair are equal, output values will not change even if a compare-match occurs. a maximum of 4-phase pwm output is possible for pwm mode 1. ? pwm mode 2 generates pwm output using one tgr register as a period register and another as a duty cycle register. the output value of each pin upon a counter clear is the initial value established by the tior register. when the values set in the period register and duty register are equal, output values will not change even if a compare-match occurs.
136 table 8.7 lists the combinations of pwm output pins and registers. table 8.7 combinations of pwm output pins and registers output pin channel register pwm mode 1 pwm mode 2 0 (ab pair) tgr0a tgr0b tioc0a tioc 0a 0 (cd pair) tgr0c tgr0d tioc0c tioc 0c 1 tgr1a tgr1b tioc1a tioc 1a tioc 1b 2 tgr2a tgr2b tioc2a tioc 2a tioc 2b note: pwm output of the period setting tgr is not possible in pwm mode 2. procedure for selecting the pwm mode (figure 8.23): 1. set bits tpsc2 to tpsc0 in the tcr to select the counter clock source. at the same time, set bits ckeg1 and ckeg0 in the tcr to select the desired edge of the input clock. 2. set bits cclr2 to cclr0 in the tcr to select the tgr to be used as a counter clear source. 3. set the period in the tgr selected in step 2, and the duty cycle in another tgr. 4. using the timer i/o control register (tior), set the tgr selected in step 3 to act as an output compare register, and select the initial value and output value. 5. set the md3 to md 0 bits in tmdr to select the pwm mode. 6. set the cst bit in the tstr to 1 to let the tcnt start counting.
137 (1) (2) (3) (4) (5) (6) pwm mode select counter clock select waveform output level set tgr select pwm mode start counting pwm mode select counter clear source figure 8.23 procedure for selecting the pwm mode pwm mode operation examples?wm mode 1 (figure 8.24): a tgra register compare- match is used as a tcnt counter clear source, the tgra register initial output value and output compare output value are both 0, and the tgrb register output compare output value is a 1. in this example, the value established in the tgra register becomes the period and the value established in the tgrb register becomes the duty cycle. counter cleared by tgra compare match tcnt value tgra tgrb h'0000 tioca time figure 8.24 pwm mode operation example (mode 1)
138 pwm mode operation examples?wm mode 2 (figure 8.25): channels 0 and 1 are set for synchronous operation, tgr1b register compare-match is used as a tcnt counter clear source, the other tgr register initial output value is 0 and output compare output value is 1, and a 3-phase pwm waveform is output. in this example, the value established in the tgr1b register becomes the period and the value established in the other tgr register becomes the duty cycle. tcntvalue counter cleared on tgr1b compare match tgr0c tgr0a tgr1b tgr1a h'0000 tioc0a tioc0c tioc1a time figure 8.25 pwm mode operation example (mode 2) 0% duty cycle: figure 8.26 shows an example of a 0% duty cycle pwm waveform output in pwm mode. tgra tcnt value tgrb rewrite tgrb time 0% duty cycle tgrb rewrite tgrb rewrite ticca figure 8.26 pwm mode operation example (0% duty cycle)
139 100% duty cycle: figure 8.27 shows an example of a 100% duty cycle pwm waveform output in pwm mode. in pwm mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of waveform for the first pulse immediately after clearing the counter. tgra tcnt value tgrb rewrite tgrb time time 100% duty cycle output does not change if period register and duty cycle register compare matches occur simultaneously output does not change if period register and duty cycle register compare matches occur simultaneously tgrb rewrite tgrb rewrite tgra tcnt value tgrb rewrite tgrb tgrb rewrite 100% duty cycle 0% duty cycle tgrb rewrite figure 8.27 pwm mode operation example (100% duty cycle)
140 8.5 interrupts 8.5.1 interrupt sources and priority ranking the mtu has two interrupt sources: tgr register compare-match/input captures, tcnt counter overflows. because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be independently enabled or disabled. when an interrupt source is generated, the corresponding status flag in the timer status register (tsr) is set to 1. if the corresponding enable/disable bit in the timer input enable register (tier) is set to 1 at this time, the mtu makes an interrupt request of the interrupt controller. the interrupt request is canceled by clearing the status flag to 0. the channel priority order can be changed with the interrupt controller. the priority ranking within a channel is fixed. for more information, see section 6, interrupt controller. table 8.8 lists the mtu interrupt sources. input capture/compare match interrupts: if the tgie bit of the timer input enable register (tier) is already set to 1 when the tgf flag in the timer status register (tsr) is set to 1 by a tgr register input capture/compare-match of any channel, an interrupt request is sent to the interrupt controller. the interrupt request is canceled by clearing the tgf flag to 0. the mtu has 8 input capture/compare-match interrupts; four each for channel 0, and two each for channels 1 and 2. overflow interrupts: if the tciev bit of the tier is already set to 1 when the tcfv flag in the tsr is set to 1 by a tcnt counter overflow of any channel, an interrupt request is sent to the interrupt controller. the interrupt request is canceled by clearing the tcfv flag to 0. the mtu has three overflow interrupts, one for each channel.
141 table 8.8 mtu interrupt sources channel interrupt source description priority * 0 tgi0a tgr0a input capture/compare-match high tgi0b tgr0b input capture/compare-match tgi0c tgr0c input capture/compare-match tgi0d tgr0d input capture/compare-match tci0v tcnt0 overflow 1 tgi1a tgr1a input capture/compare-match tgi1b tgr1b input capture/compare-match tci1v tcnt1 overflow 2 tgi2a tgr2a input capture/compare-match tgi2b tgr2b input capture/compare-match tci2v tcnt2 overflow low note: * indicates the initial status following reset. the ranking of channels can be altered using the interrupt controller. 8.5.2 a/d converter activation the tgra register input capture/compare-match of any channel can be used to activate the on- chip a/d converter. if the ttge bit of the tier is already set to 1 when the tgfa flag in the tsr is set to 1 by a tgra register input capture/compare-match of any of the channels, an a/d conversion start request is sent to the a/d converter. if the mtu conversion start trigger is selected at such a time on the a/d converter side when this happens, the a/d conversion starts. the mtu has 3 tgra register input capture/compare-match interrupts, one for each channel, that can be used as a/d converter activation sources.
142 8.6 operation timing 8.6.1 input/output timing tcnt count timing: count timing for the tcnt counter with internal clock operation is shown in figure 8.28. tcnt input clock internal clock tcnt falling edge falling edge rising edge n 1 n n + 1 n + 2 figure 8.28 tcnt count timing during internal clock operation output compare output timing: the compare-match signal is generated at the final state of tcnt and tgr matching. when a compare-match signal is issued, the output value set in tior or tocr is output to the output compare output pin (tioc pin). after tcnt and tgr matching, a compare-match signal is not issued until immediately before the tcnt input clock. output compare output timing (normal mode and pwm mode) is shown in figure 8.29.
143 tcnt input clock tioc pin compare- match signal tcnt tgr n n n + 1 figure 8.29 output compare output timing (normal mode/pwm mode) input capture signal timing: figure 8.30 illustrates input capture timing. input capture input input capture signal tcnt tgr n n + 2 n n + 2 n + 1 rising edge falling edge figure 8.30 input capture input signal timing
144 counter clearing timing due to compare-match/input capture: timing for counter clearing due to compare-match is shown in figure 8.31. figure 8.32 shows the timing for counter clearing due to input capture. compare- match signal counter clear signal tcnt tgr n n h'0000 figure 8.31 counter clearing timing (compare-match) input capture signal counter clear signal tcnt tgr n n h'0000 figure 8.32 counter clearing timing (input capture)
145 buffer operation timing: compare-match buffer operation timing is shown in figure 8.33. figure 8.34 shows input capture buffer operation timing. tcnt compare- match buffer signal tgra, tgrb tgrc, tgrd n n + 1 nn n compare- match signal figure 8.33 buffer operation timing (compare-match) tcnt input capture signal buffer tgra, tgrb tgrc, tgrd n n + 1 nn n n + 1 n input capture signal figure 8.34 buffer operation timing (input capture)
146 8.6.2 interrupt signal timing setting tgf flag timing during compare-match: figure 8.35 shows timing for the tgf flag of the timer status register (tsr) due to compare-match, as well as tgi interrupt request signal timing. compare- match signal tcnt tcnt input clock tgr tgf flag tgi interrupt n n + 1 n figure 8.35 tgi interrupt timing (compare match)
147 setting tgf flag timing during input capture: figure 8.36 shows timing for the tgf flag of the timer status register (tsr) due to input capture, as well as tgi interrupt request signal timing. input capture signal tcnt tgr tgf flag tgi interrupt n n figure 8.36 tgi interrupt timing (input capture) setting timing for overflow flag (tcfv): figure 8.37 shows timing for the tcfv flag of the timer status register (tsr) due to overflow, as well as tciv interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock tcfv flag tciv interrupt h'ffff h'0000 figure 8.37 tciv interrupt setting timing
148 status flag clearing timing: the status flag is cleared when the cpu reads a 1 status followed by a 0 write. figure 8.38 shows the timing for status flag clearing by the cpu. status flag interrupt request signal address write signal t 1 t 2 tsr write cycle tsr address figure 8.38 timing of status flag clearing by the cpu 8.7 notes and precautions this section describes contention and other matters requiring special attention during mtu operations. note on cycle setting: when setting a counter clearing by compare-match, clearing is done in the final state when tcnt matches the tgr value (update timing for count value on tcnt match). the actual number of states set in the counter is given by the following equation: f = (n + 1) (f: counter frequency, : operating frequency, n: value set in the tgr) contention between tcnt write and clear: if a counter clear signal is issued in the t 2 state during the tcnt write cycle, tcnt clearing has priority, and tcnt write is not conducted (figure 8.39).
149 counter clear signal tcnt address write signal t 1 t 2 tcnt write cycle tcnt address n h'0000 figure 8.39 tcnt write and clear contention contention between tcnt write and increment: if a count-up signal is issued in the t 2 state during the tcnt write cycle, tcnt write has priority, and the counter is not incremented (figure 8.40). tcnt input clock tcnt address write signal t 1 t 2 tcnt write cycle tcnt write data tcnt address m n figure 8.40 tcnt write and increment contention
150 contention between buffer register write and compare match: if a compare-match occurs in the t 2 state of the tgr write cycle, data is transferred by the buffer operation from the buffer register to the tgr. on channel 0, the data to be transferred is that after the write (figure 8.41). buffer register compare match signal compare match buffer signal address write signal tgr t 1 t 2 tgr write cycle buffer register address nm buffer register write data m figure 8.41 tgr write and compare-match contention (channel 0)
151 contention between tgr read and input capture: if an input capture signal is issued in the t 1 state of the tgr read cycle, the read data is that after input capture transfer (figure 8.42). tgr input capture signal internal data bus address read signal t 1 t 2 tgr read cycle tgr address m xm figure 8.42 tgr read and input capture contention
152 contention between tgr write and input capture: if an input capture signal is issued in the t 2 state of the tgr read cycle, input capture has priority, and tgr write does not occur (figure 8.43). tgr input capture signal tcnt address write signal t 1 t 2 tgr write cycle tgr address m m figure 8.43 tgr write and input capture contention
153 contention between buffer register write and input capture: if an input capture signal is issued in the t 2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 8.44). tgr input capture signal tcnt address write signal buffer register t 1 t 2 buffer register write cycle buffer register address n mn m figure 8.44 buffer register write and input capture contention
154 contention between tgr write and compare match: if a compare-match occurs in the t 2 state of the tgr write cycle, data is written to the tgr and a compare-match signal is issued (figure 8.45). tgr compare match signal tcnt address write signal t 1 t 2 tgr write cycle tgr address n n + 1 m n tgr write data figure 8.45 tgr write and compare match contention tcnt2 write and overflow contention in cascade connection: with timer counters tcnt1 and tcnt2 in a cascade connection, when a contention occurs during tcnt1 count (during a tcnt2 overflow) in the t 2 state of the tcnt2 write cycle, the write to tcnt2 is conducted, and the tcnt1 count signal is prohibited. at this point, if there is match with tgr1a and the tcnt1 value, a compare signal is issued. when the tcnt1 count clock is selected as the channel 0 input capture source, tgr0a and tgr0c operate as input capture registers. when tgr0c compare- match/input capture is selected as the tgr1b input capture source, tgr1b operates as an input capture register. the timing is shown in figure 8.46. for cascade connections, be sure to synchronize settings for channels 1 and 2 when setting tcnt clearing.
155 t1 t2 h'fffe h'ffff n n + 1 h'ffff m m n p qp m disabled tcnt2 write data tcnt2 address tcnt write cycle address write signal tcnt2 tgr2a to b ch2 compare- match signal a/b tcnt1 input clock tcnt1 tgr1a ch1 compare- match signal a tgr1b ch1 inputcapture signal b tcnt0 tgr0a to d ch0 input capture signal a, c figure 8.46 tcnt2 write and overflow contention with cascade connection
156 contention between overflow and counter clearing: if overflow and counter clearing occur simultaneously, the tcfv flag in tsr is not set and tcnt clearing takes precedence. figure 8.47 shows the operation timing when a tgr compare-match is specified as the clearing source, and h'ffff is set in tgr. tcnt input clock tcnt counter clear signal tgf flag tcfv flag h'ffff h'0000 disabled figure 8.47 contention between overflow and counter clearing contention between tcnt write and overflow: if there is an up-count in the t2 state of a tcnt write cycle, and overflow occurs, the tcnt write takes precedence and the tcfv flag in tsr is not set .
157 figure 8.48 shows the operation timing in this case. address write signal tcnt input clock tcnt tcfv flag h'ffff n tcnt write data disabled tcnt write cycle t1 t2 tcnt address figure 8.48 contention between tcnt write and overflow 8.8 mtu output pin initialization 8.8.1 operating modes the mtu has the following three operating modes. waveform output is possible in all of these modes. ? normal mode (channels 0 to 2) ? pwm mode 1 (channels 0 to 2) ? pwm mode 2 (channels 0 to 2) the mtu output pin initialization method for each of these modes is described in this section.
158 8.8.2 reset start operation the mtu output pins (tioc*) are initialized low by a reset and in standby mode. since mtu pin function selection is performed by the pin function controller (pfc), when the pfc is set, the mtu pin states at that point are output to the ports. when mtu output is selected by the pfc immediately after a reset, the mtu output initial level, low, is output directly at the port. when the active level is low, the system will operate at this point, and therefore the pfc setting should be made after initialization of the mtu output pins is completed. note: * represents the channel number and port symbol. 8.8.3 operation in case of re-setting due to error during operation, etc. if an error occurs during mtu operation, mtu output should be cut by the system. cutoff is performed by switching the pin output to port output with the pfc and outputting the inverse of the active level. the pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. the mtu has three operating modes, as stated above. there are thus 9 mode transition combinations. possible mode transition combinations are shown in table 8.9. table 8.9 mode transition combinations after before normal pwm1 pwm2 normal (1) (2) (3) pwm1 (4) (5) (6) pwm2 (7) (8) (9) legend: normal: normal mode pwm1: pwm1 mode pwm2: pwm2 mode the above abbreviations are used in some places in the following descriptions.
159 8.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. ? when making a transition to a mode (normal, pwm1, pwm2) in which the pin output level is selected by the timer i/o control register (tior) setting, initialize the pins by means of a tior setting. ? in pwm mode 1, since a waveform is not output to the tioc*b pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 1. ? in pwm mode 2, since a waveform is not output to the cycle register pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 2. ? in normal mode or pwm mode 2, if tgrc and tgrd operate as buffer registers, setting tior will not initialize the buffer register pins. if initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. ? in pwm mode 1, if either tgrc or tgrd operates as a buffer register, setting tior will not initialize the tgrc pin. to initialize the tgrc pin, clear buffer mode, carry out initialization, then set buffer mode again. note: an asterisk in this section represents the channel number. pin initialization procedures are described below for the numbered combinations in table 8.9. the active level is assumed to be low.
160 (1) operation when error occurs during normal mode operation, and operation is restarted in normal mode: figure 8.49 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output n = 0, 2, 4 to 7, 12 to 14 tioc*a tioc*b port output pen pen z z figure 8.49 error occurrence in normal mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. after a reset, the tmdr setting is for normal mode. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. not necessary when restarting in normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr.
161 (2) operation when error occurs during normal mode operation, and operation is restarted in pwm mode 1: figure 8.50 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output n = 0, 2, 4 to 7, 12 to 14 tioc * a tioc * b port output pen pen z z not initialized (to * b) figure 8.50 error occurrence in normal mode, recovery in pwm mode 1 1 to 9 are the same as in figure 8.49. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the to*b side is not initialized. if initialization is required, initialize in normal mode, then switch to pwm mode 1.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
162 (3) operation when error occurs during normal mode operation, and operation is restarted in pwm mode 2: figure 8.51 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior ("1"init "0"out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output n = 0, 2, 4 to 7, 12 to 14 tioc * a tioc * b port output pen pen z z not initialized (cycle register) figure 8.51 error occurrence in normal mode, recovery in pwm mode 2 1 to 9 are the same as in figure 8.49. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized. if initialization is required, initialize in normal mode, then switch to pwm mode 2.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
163 (4) operation when error occurs during pwm mode 1 operation, and operation is restarted in normal mode: figure 8.52 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen z z not initialized (tioc * b) n = 0, 2, 4 to 7, 12 to 14 figure 8.52 error occurrence in pwm mode 1, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set pwm mode 1. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 1, the tioc*b side is not initialized.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr.
164 (5) operation when error occurs during pwm mode 1 operation, and operation is restarted in pwm mode 1: figure 8.53 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen z z not initialized (tioc * b) not initialized (tioc*b) n = 0, 2, 4 to 7, 12 to 14 figure 8.53 error occurrence in pwm mode 1, recovery in pwm mode 1 1 to 9 are the same as in figure 8.52. 10. not necessary when restarting in pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
165 (6) operation when rrror occurs during pwm mode 1 operation, and operation is restarted in pwm mode 2: figure 8.54 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen z z not initialized (tioc * b) not initialized (cycle register) n = 0, 2, 4 to 7, 12 to 14 figure 8.54 error occurrence in pwm mode 1, recovery in pwm mode 2 1 to 9 are the same as in figure 8.52. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
166 (7) operation when error occurs during pwm mode 2 operation, and operation is restarted in normal mode: figure 8.55 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen z z not initialized (cycle register) n = 0, 2, 4 to 7, 12 to 14 figure 8.55 error occurrence in pwm mode 2, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set pwm mode 2. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 2, the cycle register pins are not initialized. in the example, tioc*a is the cycle register.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr.
167 (8) operation when error occurs during pwm mode 2 operation, and operation is restarted in pwm mode 1: figure 8.56 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen z z not initialized (tioc * b) not initialized (cycle register) n = 0, 2, 4 to 7, 12 to 14 figure 8.56 error occurrence in pwm mode 2, recovery in pwm mode 1 1 to 9 are the same as in figure 8.55. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
168 (9) operation when error occurs during pwm mode 2 operation, and operation is restarted in pwm mode 2: figure 8.57 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen z z not initialized (cycle register) not initialized (cycle register) n = 0, 2, 4 to 7, 12 to 14 figure 8.57 error occurrence in pwm mode 2, recovery in pwm mode 2 1 to 9 are the same as in figure 8.55. 10. not necessary when restarting in pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
169 section 9 8-bit timer 2 (tim2) 9.1 overview 8-bit timer 2 (tim2) is a single-channel interval timer that generates compare match interrupts. 9.1.1 features ? 8-bit interval timer ? generates compare match interrupts a compare match interrupt is generated by a counter compare match. ? selection of seven counter input clock sources
170 9.1.2 block diagram figure 9.1 shows a block diagram of 8-bit timer 2 (tim2). interrupt control clock clock selection cmi (interrupt request signal) comparator t2cnt t2cor t2csr module bus internal bus bus interface /2 /8 /32 /128 /512 /2048 /4096 8-bit timer 2 t2csr: t2cnt: t2cor: timer 2 control/status register timer 2 counter timer 2 constant register figure 9.1 block diagram of 8-bit timer 2 9.1.3 register configuration 8-bit timer 2 (tim2) has three registers for compare match cycle setting, clock selection, and other functions. the register configuration is shown in table 9.1. all the registers are 16 bits in size, and are initialized by a power-on reset.
171 table 9.1 8-bit timer 2 registers name abbreviation r/w initial value address access size timer 2 control/status register t2csr r/w h'0000 h'ffff862c 8, 16, 32 timer 2 counter t2cnt r/w h'0000 h'ffff862e 8, 16, 32 timer 2 constant register t2cor r/w h'0000 h'ffff8630 8, 16 9.2 register descriptions 9.2.1 timer 2 control/status register (t2csr) the timer 2 control/status register (t2csr) is a 16-bit readable/writable* register that selects the clock to be input to the timer 2 counter (t2cnt) and controls compare match interrupts (cmi). t2csr is initialized to h'0000 by a power-on reset. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cmf cmie cks2 cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r r ? bits 15 to 7?eserved: these bits are always read as 0. the write value should always be 0. ? bit 6?ompare match flag (cmf): status flag that indicates a match between the values of t2cnt and t2cor. the setting and clearing conditions for this flag are shown below. bit 6: cmf description 0 [clearing condition] cleared by reading t2csr when cmf = 1, then writing 0 in cmf (initial value) 1 [setting condition] set when t2cnt = t2cor * note: * when t2cnt and t2cor still contain their initial values (when the initial values have not been changed or when the t2cnt value has not been incremented), cmf is not set even though the t2cnt and t2cor values are the same (h'0000).
172 ? bit 5?ompare match interrupt enable (cmie): enables or disables interrupt requests initiated by the cmf flag when set to 1 in t2csr. bit 5: cmie description 0 interrupt request by cmf flag disabled (initial value) 1 interrupt request by cmf flag enabled ? bits 4 to 2?lock select 2 to 0 (cks2 to cks0): these bits select one of seven internal clock sources, obtained by dividing the system clock ( ), for input to t2cnt. bit 4: cks2 bit 3: cks1 bit 2: cks0 description 0 0 0 up-count stopped (initial value) 1 /2 10 /8 1 /32 100 /128 1 /512 10 /2048 1 /4096 ? bits 1 and 0?eserved: these bits are always read as 0. the write value should always be 0. 9.2.2 timer 2 counter (t2cnt) the timer 2 counter (t2cnt) is a 16-bit readable/writable register used as an 8-bit up-counter. t2cnt increments on the internal clock selected by bits cks2 to cks0 in t2csr. the t2cnt value can be read or written by the cpu at all times. when the t2cnt value matches the value in the timer 2 constant register (t2cor), t2cnt is cleared to h'0000 and the cmf flag is set to 1 in t2csr. if the cmie bit in t2csr is set to 1 at this time, a compare match interrupt (cmi) is generated. bits 15 to 8 are reserved and have no counter function. these bits are always read as 0. the write value should always be 0. t2cnt is initialized to h'0000 by a power-on reset.
173 bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 9.2.3 timer 2 constant register (t2cor) the timer 2 constant register (t2cor) is a 16-bit readable/writable register that is used to set the t2cnt compare match cycle. the values in t2cor and t2cnt are continually compared, and when the values match the cmf flag is set in t2csr and t2cnt is cleared to 0. if the cmie bit in t2csr is set to 1, an interrupt request is sent to the interrupt controller in response to the match signal. the interrupt request is output continuously until the cmf flag in t2csr is cleared. bits 15 to 8 are reserved and are not used in the cycle setting. these bits are always read as 0. the write value should always be 0. t2cor is initialized to h'0000 by a power-on reset. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
174 9.3 operation 9.3.1 cyclic count operation when a clock is selected with bits cks2 to cks0 in the t2csr register, the t2cnt counter starts incrementing on the selected clock. when the t2cnt counter value matches the value in the timer 2 constant register (t2cor), the t2cnt counter is cleared to h'00, and the cmf flag is set to 1 in the t2csr register. if the cmie bit in t2csr is set to 1 at this time, a compare match interrupt (cmi) is requested. the t2cnt counter then starts incrementing again from h'00. the compare match counter operation is shown in figure 9.2. t2cnt value t2cor h'00 counter cleared by t2cor compare match time figure 9.2 counter operation 9.3.2 t2cnt count timing any of seven internal clocks ( /2, /8, /32, /128, /512, /2048, or /4096) divided from the system clock (ck) can be selected with bits cks2 to cks0 in t2csr. the count timing is shown in figure 9.3. ck internal clock t2cnt input clock t2cnt n 1 n n + 1 figure 9.3 count timing
175 9.4 interrupts 9.4.1 interrupt source when interrupt request flag cmf is set to 1, and interrupt enable bit cmie is also 1, the corresponding interrupt request is output. 9.4.2 timing of compare match flag setting the cmf bit in the t2csr register is set to 1 by the compare match signal generated when the t2cor register and t2cnt counter values match. the compare match signal is generated in the last state in which the match is true (when the value at which the t2cnt counter match occurred is about to be updated). therefore, after a match between the t2cnt counter and the t2cor register, the compare match signal is not generated until the next t2cnt counter input clock pulse. figure 9.4 shows the timing of cmf bit setting. ck t2cnt input clock pulse t2cnt t2cor n0 n compare match signal cmf cmi figure 9.4 timing of cmf setting
176 9.4.3 timing of compare match flag clearing the cmf bit in the t2csr register is cleared by reading the bit when it is set to 1, then writing 0 in it. figure 9.5 shows the timing of cmf bit clearing by the cpu. t1 t2 t2csr write cycle ck cmf figure 9.5 timing of cmf clearing by cpu
177 section 10 compare match timer (cmt) 10.1 overview the SH7018 has an on-chip compare match timer (cmt) configured of 16-bit timers for two channels. the cmt has 16-bit counters and can generate interrupts at set intervals. 10.1.1 features the cmt has the following features: ? four types of counter input clock can be selected ? one of four internal clocks ( /8, /32, /128, /512) can be selected independently for each channel. ? interrupt sources ? a compare match interrupt can be requested independently for each channel.
178 10.1.2 block diagram figure 10.1 shows a block diagram of the cmt. cmi0 control circuit internal bus clock selection control circuit clock selection cmi1 /8 /32 /128 /512 /8 /32 /128 /512 cmcsr1 cmcor1 cmcnt1 cmcnt0 cmcor0 comparator cmstr cmcsr0 comparator bus interface module bus cmt cmstr: cmcsr: cmcor: cmcnt: cmi: compare match timer start register compare match timer control/status register compare match timer constant register compare match timer counter compare match interrupt figure 10.1 cmt block diagram
179 10.1.3 register configuration table 10.1 summarizes the cmt register configuration. table 10.1 register configuration channel name abbreviation r/w initial value address access size (bits) shared compare match timer start register cmstr r/w h'0000 h'ffff83d0 8, 16, 32 0 compare match timer control/status register 0 cmcsr0 r/(w) * h'0000 h'ffff83d2 8, 16, 32 compare match timer counter 0 cmcnt0 r/w h'0000 h'ffff83d4 8, 16, 32 compare match timer constant register 0 cmcor0 r/w h'ffff h'ffff83d6 8, 16, 32 1 compare match timer control/status register 1 cmcsr1 r/(w) * h'0000 h'ffff83d8 8, 16, 32 compare match timer counter 1 cmcnt1 r/w h'0000 h'ffff83da 8, 16, 32 compare match timer constant register 1 cmcor1 r/w h'ffff h'ffff83dc 8, 16 note: * the only value that can be written to the cmcsr0 and cmcsr1 cmf bits is a 0 to clear the flags.
180 10.2 register descriptions 10.2.1 compare match timer start register (cmstr) the compare match timer start register (cmstr) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (cmcnt). it is initialized to h'0000 by power-on resets. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 str1 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w ? bits 15 to 2?eserved: these bits are always read as 0. the write value should always be 0. ? bit 1?ount start 1 (str1): selects whether to operate or halt compare match timer counter 1 (cmcnt1). bit 1: str1 description 0 cmcnt1 count operation halted (initial value) 1 cmcnt1 count operation ? bit 0?ount start 0 (str0): selects whether to operate or halt compare match timer counter 0 (cmcnt0). bit 0: str0 description 0 cmcnt0 count operation halted (initial value) 1 cmcnt0 count operation
181 10.2.2 compare match timer control/status register (cmcsr) the compare match timer control/status register (cmcsr) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. it is initialized to h'0000 by power-on resets. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cmf cmie cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w) * r/w r r r r r/w r/w note: * the only value that can be written is a 0 to clear the flag. ? bits 15 to 8 and 5 to 2?eserved: these bits are always read as 0. the write value should always be 0. ? bit 7?ompare match flag (cmf): this flag indicates whether or not the cmcnt and cmcor values have matched. bit 7: cmf description 0 cmcnt and cmcor values have not matched (initial value) clear condition: write a 0 to cmf after reading a 1 from it 1 cmcnt and cmcor values have matched ? bit 6?ompare match interrupt enable (cmie): selects whether to enable or disable a compare match interrupt (cmi) when the cmcnt and cmcor values have matched (cmf = 1). bit 6: cmie description 0 compare match interrupts (cmi) disabled (initial value) 1 compare match interrupts (cmi) enabled
182 ? bits 1 and 0?lock select 1 and 0 (cks1, cks0): these bits select the clock input to the cmcnt from among the four internal clocks obtained by dividing the system clock ( ). when the str bit of the cmstr is set to 1, the cmcnt begins incrementing with the clock selected by cks1 and cks0. bit 1: cks1 bit 0: cks0 description 00 /8 (initial value) 1 /32 10 /128 1 /512 10.2.3 compare match timer counter (cmcnt) the compare match timer counter (cmcnt) is a 16-bit register used as an upcounter for generating interrupt requests. when an internal clock is selected with the cks1, cks0 bits of the cmcsr register and the str bit of the cmstr is set to 1, the cmcnt begins incrementing with that clock. when the cmcnt value matches that of the compare match timer constant register (cmcor), the cmcnt is cleared to h'0000 and the cmf flag of the cmcsr is set to 1. if the cmie bit of the cmcsr is set to 1 at this time, a compare match interrupt (cmi) is requested. the cmcnt is initialized to h'0000 by power-on resets. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
183 10.2.4 compare match timer constant register (cmcor) the compare match timer constant register (cmcor) is a 16-bit register that sets the compare match period with the cmcnt. the cmcor is initialized to h'ffff by power-on resets. bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 10.3 operation 10.3.1 period count operation when an internal clock is selected with the cks1, cks0 bits of the cmcsr register and the str bit of the cmstr is set to 1, the cmcnt begins incrementing with the selected clock. when the cmcnt counter value matches that of the compare match constant register (cmcor), the cmcnt counter is cleared to h'0000 and the cmf flag of the cmcsr register is set to 1. if the cmie bit of the cmcsr register is set to 1 at this time, a compare match interrupt (cmi) is requested. the cmcnt counter begins counting up again from h'0000. figure 10.2 shows the compare match counter operation. cmcor h'0000 cmcnt value time counter cleared by cmcor compare match figure 10.2 counter operation
184 10.3.2 cmcnt count timing one of four clocks ( /8, /32, /128, /512) obtained by dividing the system clock (ck) can be selected by the cks1 and cks0 bits of the cmcsr. figure 10.3 shows the timing. ck n 1 n n + 1 internal clock cmcnt input clock cmcnt figure 10.3 count timing 10.4 interrupts 10.4.1 interrupt sources the cmt has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. the corresponding interrupt request is output when the interrupt request flag cmf is set to 1 and the interrupt enable bit cmie has also been set to 1. when activating cpu interrupts by interrupt request, the priority between the channels can be changed by using the interrupt controller settings. see section 6, interrupt controller, for details. 10.4.2 compare match flag set timing the cmf bit of the cmcsr register is set to 1 by the compare match signal generated when the cmcor register and the cmcnt counter match. the compare match signal is generated upon the final state of the match (timing at which the cmcnt counter matching count value is updated). consequently, after the cmcor register and the cmcnt counter match, a compare match signal will not be generated until a cmcnt counter input clock occurs. figure 10.4 shows the cmf bit set timing.
185 ck cmcnt input clock cmcnt cmcor compare match signal cmf cmi n n 0 figure 10.4 cmf set timing 10.4.3 compare match flag clear timing the cmf bit of the cmcsr register is cleared either by writing a 0 to it after reading a 1. figure 10.5 shows the timing when the cmf bit is cleared by the cpu. t 2 t 1 ck cmf cmcsr write cycle figure 10.5 timing of cmf clear by the cpu
186 10.5 notes on use take care that the contentions described in sections 10.5.1 to 10.5.3 do not arise during cmt operation. 10.5.1 contention between cmcnt write and compare match if a compare match signal is generated during the t 2 state of the cmcnt counter write cycle, the cmcnt counter clear has priority, so the write to the cmcnt counter is not performed. figure 10.6 shows the timing. t 1 t 2 ck address internal write signal compare match signal cmcnt cmcnt write cycle cmcnt n h'0000 figure 10.6 cmcnt write and compare match contention
187 10.5.2 contention between cmcnt word write and incrementation if an increment occurs during the t 2 state of the cmcnt counter word write cycle, the counter write has priority, so no increment occurs. figure 10.7 shows the timing. cmcnt write data t 1 t 2 ck address internal write signal compare match signal cmcnt cmcnt write cycle cmcnt nm figure 10.7 cmcnt word write and increment contention
188 10.5.3 contention between cmcnt byte write and incrementation if an increment occurs during the t 2 state of the cmcnt byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. the byte data on the side not performing the writing is also not incremented, so the contents are those before the write. figure 10.8 shows the timing when an increment occurs during the t 2 state of the cmcnth write cycle. t 1 t 2 ck address internal write signal cmcnt input clock cmcnth cmcnt write cycle cmcnth n m cmcnth write data x x cmcntl figure 10.8 cmcnt byte write and increment contention
189 section 11 watchdog timer (wdt) 11.1 overview the watchdog timer (wdt) is a 1-channel timer for monitoring system operations. if the wdt overflows without being rewritten correctly by the cpu due to system runaway or the like, it can generate an internal reset signal for the chip. when the watchdog function is not needed, the wdt can be used as an interval timer. in the interval timer operation, an interval timer interrupt is generated at each counter overflow. the wdt is also used in recovering from the standby mode. 11.1.1 features ? works in watchdog timer mode or interval timer mode. ? if the counter overflows in the watchdog timer mode, wdt can generate an internal reset signal for the chip. ? generates interrupts in the interval timer mode. when the counter overflows, it generates an interval timer interrupt. ? clears standby mode. ? works with eight counter input clocks.
190 11.1.2 block diagram figure 11.1 is the block diagram of the wdt. /2 /64 /128 /256 /512 /1024 /4096 /8192 internal clock sources clock overflow clock select interrupt control reset control rstcsr tcsr: tcnt: rstcsr: note: * timer control/status register timer counter reset control/status register the internal reset signal can be generated by setting the register. tcnt tcsr module bus bus interface internal data bus iti (interrupt signal) internal reset signal * wdt figure 11.1 wdt block diagram
191 11.1.3 register configuration table 11.1 summarizes the three wdt registers. they are used to select the clock, switch the wdt mode, and control the reset signal. table 11.1 wdt registers address name abbreviation r/w initial value write * 1 read * 2 timer control/status register tcsr r/(w) * 3 h'18 h'ffff8610 h'ffff8610 timer counter tcnt r/w h'00 h'ffff8611 reset control/status register rstcsr r/(w) * 3 h'1f h'ffff8612 h'ffff8613 notes: 1. write by word transfer. it cannot be written in byte or longword. 2. read by byte transfer. it cannot be read in word or longword. 3. only 0 can be written in bit 7 to clear the flag. 11.2 register descriptions 11.2.1 timer counter (tcnt) the tcnt is an 8-bit read/write upcounter. (the tcnt differs from other registers in that it is more difficult to write to. see section 11.2.4, register access, for details.) when the timer enable bit (tme) in the timer control/status register (tcsr) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to 0 (cks2 to cks0) in the tcsr. when the value of the tcnt overflows (changes from h'ff to h'00), an internal reset signal from the watchdog timer* or interval timer interrupt (iti) is generated, depending on the mode selected in the wt/ it bit of the tcsr. the tcnt is initialized to h'00 by a power-on reset and when the tme bit is cleared to 0. it is not initialized in the standby mode. note: * if rste of rstcsr is set to 1. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
192 11.2.2 timer control/status register (tcsr) the timer control/status register (tcsr) is an 8-bit read/write register. (the tcsr differs from other registers in that it is more difficult to write to. see section 11.2.4, register access, for details.) its functions include selecting the clock input source and mode of the timer counter (tcnt). bits 7 to 5 are initialized to 000 by a power-on reset or in standby mode. bits 2 to 0 are initialized to 000 by a power-on reset, but retain their values in the standby mode. bit: 7 6 5 4 3 2 1 0 ovf wt/ it tme cks2 cks1 cks0 initial value: 0 0 0 1 1 0 0 0 r/w: r/(w) r/w r/w r r r/w r/w r/w ? bit 7?verflow flag (ovf): indicates that the tcnt has overflowed from h'ff to h'00 in the interval timer mode. it is not set in the watchdog timer mode. bit 7: ovf description 0 no overflow of tcnt in interval timer mode (initial value) cleared by reading ovf, then writing 0 in ovf 1 tcnt overflow in the interval timer mode ? bit 6?imer mode select (wt/ ): selects whether to use the wdt as a watchdog timer or interval timer. bit 6: wt/ it description 0 interval timer mode (initial value) 1 watchdog timer mode: wdtovf signal output externally when tcnt overflows. (section 11.2.3, reset control/status register (rstcsr), describes in detail what happens when tcnt overflows in the watchdog timer mode.) ? bit 5?imer enable (tme): enables or disables the timer. bit 5: tme description 0 timer disabled: tcnt is initialized to h'00 and count-up stops (initial value) 1 timer enabled: tcnt starts counting. ? bits 4 and 3?eserved: these bits are always read as 1. the write value should always be 1.
193 ? bits 2 to 0: clock select 2 to 0 (cks2 to cks0): these bits select one of eight internal clock sources for input to the tcnt. the clock signals are obtained by dividing the frequency of the system clock ( ). description bit 2: cks2 bit 1: cks1 bit 0: cks0 clock source overflow interval * ( = 20.0 mhz) 00 0 /2 (initial value) 25.6 ? 1 /64 819.2 ? 10 /128 1.6384 ms 1 /256 3.2768 ms 10 0 /512 6.5536 ms 1 /1024 13.1072 ms 10 /4096 52.4288 ms 1 /8192 104.8576 ms note: * the overflow interval listed is the time from when the tcnt begins counting at h'00 until an overflow occurs. 11.2.3 reset control/status register (rstcsr) the rstcsr is an 8-bit readable and writable register. (the rstcsr differs from other registers in that it is more difficult to write. see section 11.2.4, register access, for details.) it controls output of the internal reset signal generated by timer counter (tcnt) overflow and selects the internal reset signal type. rstcr is initialized to h'1f by input of a reset signal from the res pin, but is not initialized by the internal reset signal generated by the overflow of the wdt. it is initialized to h'1f in standby mode. bit: 7 6 5 4 3 2 1 0 wovf rste initial value: 0 0 0 1 1 1 1 1 r/w: r/(w) * r/wrrrrrr note: * only 0 can be written in bit 7 to clear the flag. ? bit 7?atchdog timer overflow flag (wovf): indicates that the tcnt has overflowed (h'ff to h'00) in the watchdog timer mode. it is not set in the interval timer mode.
194 bit 7: wovf description 0 no tcnt overflow in watchdog timer mode (initial value) cleared when software reads wovf, then writes 0 in wovf 1 set by tcnt overflow in watchdog timer mode ? bit 6?eset enable (rste): selects whether to reset the chip internally if the tcnt overflows in the watchdog timer mode. bit 6: rste description 0 not reset when tcnt overflows (initial value) lsi not reset internally, but tcnt and tcsr reset within wdt. 1 reset when tcnt overflows ? bit 5?eserved: this bit is always read as 0. the write value should always be 0. ? bits 4 to 0?eserved: these bits are always read as 1. the write value should always be 1. 11.2.4 register access the watchdog timer? tcnt, tcsr, and rstcsr registers differ from other registers in that they are more difficult to write to. the procedures for writing and reading these registers are given below. writing to the tcnt and tcsr: these registers must be written by a word transfer instruction. they cannot be written by byte transfer instructions. the tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must be h'5a (for the tcnt) or h'a5 (for the tcsr) (figure 11.2). this transfers the write data from the lower byte to the tcnt or tcsr. h'5a h'ffff8610 address: writing to the tcnt 15 8 7 0 write data h'a5 h'ffff8610 address: writing to the tcsr 15 8 7 0 write data figure 11.2 writing to the tcnt and tcsr
195 writing to the rstcsr: the rstcsr must be written by a word access to address h'ffff8612. it cannot be written by byte transfer instructions. procedures for writing 0 in wovf (bit 7) and for writing to rste (bit 6) and rsts (bit 5) are different, as shown in figure 11.3. to write 0 in the wovf bit, the write data must be h'a5 in the upper byte and h'00 in the lower byte. this clears the wovf bit to 0. the rste and rsts bits are not affected. to write to the rste and rsts bits, the upper byte must be h'5a and the lower byte must be the write data. the values of bits 6 and 5 of the lower byte are transferred to the rste and rsts bits, respectively. the wovf bit is not affected. h'a5 h'ffff8612 address: writing 0 to the wovf bit 15 8 7 0 h'00 h'5a h'ffff8612 address: writing to the rste and rsts bits 15 8 7 0 write data figure 11.3 writing to the rstcsr reading from the tcnt, tcsr, and rstcsr: tcnt, tcsr, and rstcsr are read like other registers. use byte transfer instructions. the read addresses are h'ffff8610 for the tcsr, h'ffff8611 for the tcnt, and h'ffff8613 for the rstcsr. 11.3 operation 11.3.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ it and tme bits of the tcsr to 1. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. no tcnt overflows will occur while the system is operating normally, but if rste of rstcsr is set to 1 and a problem such as system runaway occurs, the value of tcnt is not overwritten and an overflow results. this causes wdt to generate an internal reset signal for the chip. the internal reset signal is output for 512 clock cycles. figure 11.4 shows the timing. when a watchdog overflow reset is generated simultaneously with a reset input at the res pin, the res reset takes priority, and the wovf bit is cleared to 0. the following are not initialized a wdt reset signal:
196 ? pfc (pin function controller) function register ? i/o port register initializing is only possible by external power-on reset. h'ff h'00 overflow wt/ it = 1 tme = 1 h'00 written in tcnt internal reset signal * tcnt value internal reset generated wovf = 1 wt/ it = 1 tme = 1 wt/ it : tme: timer mode select bit timer enable bit h'00 written in tcnt time 512 clocks note: * internal reset signal occurs only when the rste bit is set to 1. figure 11.4 operation in the watchdog timer mode
197 11.3.2 interval timer mode to use the wdt as an interval timer, clear wt/ it to 0 and set tme to 1. an interval timer interrupt (iti) is generated each time the timer counter overflows. this function can be used to generate interval timer interrupts at regular intervals (figure 11.5). h'ff tcnt value iti: interval timer interrupt request generation h'00 wt/ it = 0 tme = 1 iti iti iti iti time overflow overflow overflow overflow figure 11.5 operation in the interval timer mode 11.3.3 clearing the standby mode the watchdog timer has a special function to clear the standby mode with an nmi interrupt. when using the standby mode, set the wdt as described below. before transition to the standby mode: the tme bit in the tcsr must be cleared to 0 to stop the watchdog timer counter before it enters the standby mode. the chip cannot enter the standby mode while the tme bit is set to 1. set bits cks2 to cks0 so that the counter overflow interval is equal to or longer than the oscillation settling time. see section 19.3, ac characteristics, for the oscillation settling time. recovery from the standby mode: when an nmi request signal is received in standby mode, the clock oscillator starts running and the watchdog timer starts incrementing at the rate selected by bits cks2 to cks0 before the standby mode was entered. when the tcnt overflows (changes from h'ff to h'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and the standby mode ends. for details on the standby mode, see section 18, power down state.
198 11.3.4 timing of setting the overflow flag (ovf) in the interval timer mode, when the tcnt overflows, the ovf flag of the tcsr is set to 1 and an interval timer interrupt is simultaneously requested (figure 11.6). h'ff h'00 ck tcnt overflow signal (internal signal) ovf figure 11.6 timing of setting the ovf 11.3.5 timing of setting the watchdog timer overflow flag (wovf) if the timer counter (tcnt) overflows in the watchdog timer mode, the wovf bit of the reset control/status register (rstcsr) is set to 1. if the rste bit of rstcsr is set to 1, an internal reset for the entire chip is generated when tcnt overflows. figure 11.7 shows the timing. h'ff h'00 ck tcnt overflow signal (internal signal) wovf figure 11.7 timing of setting the wovf bit
199 11.4 notes on use 11.4.1 tcnt write and increment contention if a timer counter (tcnt) increment clock pulse is generated during the t 3 state of a write cycle to the tcnt, the write takes priority and the timer counter is not incremented (figure 11.8). ck address internal write signal tcnt input clock tcnt nm tcnt address counter write data t 1 t 2 t 3 tcnt write cycle figure 11.8 contention between tcnt write and increment 11.4.2 changing cks2 to cks0 bit values if the values of bits cks2 to cks0 are altered while the wdt is running, the count may increment incorrectly. always stop the watchdog timer (by clearing the tme bit to 0) before changing the values of bits cks2 to cks0. 11.4.3 changing between watchdog timer/interval timer modes to prevent incorrect operation, always stop the watchdog timer (by clearing the tme bit to 0) before switching between interval timer mode and watchdog timer mode. 11.4.4 internal reset with the watchdog timer if the rste bit is cleared to 0 in the watchdog timer mode, the lsi will not reset internally when a tcnt overflow occurs, but the tcnt and tcsr in the wdt will reset.
200
201 section 12 serial communication interface (sci1) 12.1 overview the SH7018 has a serial communication interface (sci1) with one channel. the sci supports asynchronous serial communication. it also has a multiprocessor communication function for serial communication among two or more processors. 12.1.1 features ? select asynchronous or clock synchronous as the serial communications mode. ? asynchronous mode: serial data communications are synched by start-stop in character units. the sci1 can communicate with a universal asynchronous receiver/transmitter (uart), an asynchronous communication interface adapter (acia), or any other chip that employs a standard asynchronous serial communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve selectable serial data communication formats. data length: seven or eight bits stop bit length: one or two bits parity: even, odd, or none multiprocessor bit: one or none receive error detection: parity, overrun, and framing errors break detection: by reading the rxd level directly when a framing error occurs ? clock synchronous mode: serial data transfer is synchronized with the clock. this permits serial data communications with other lsi devices equipped with a clock synchronous communications function. one serial data communications format is supported. number of data bits: 8 receive error detection: over-line error detection ? full duplex communication: the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. ? on-chip baud rate generator with selectable bit rates. ? internal transmit/receive clock source: baud rate generator (internal). ? four types of interrupts: transmit-data-empty, transmit-end, receive-data-full, and receive- error interrupts are requested independently.
202 12.1.2 block diagram figure 12.1 shows a block diagram of the sci1. parity generation parity check external clock transmit/ receive control baud rate generator clock bus interface internal data bus rxd rdr1 tdr1 rsr1 tsr1 ssr1 scr1 smr1 brr1 /4 /16 /64 tei txi rxi eri : : : : rsr1 rdr1 tsr1 tdr1 receive shift register receive data register transmit shift register transmit data register : : : : smr1 scr1 ssr1 brr1 serial mode register serial control register serial status register bit rate register txd sck sci1 module data bus figure 12.1 sci1 block diagram 12.1.3 pin configuration table 12.1 summarizes the sci1 pins by channel. table 12.1 sci1 pins pin name abbreviation input/output function serial clock pin sck input/output sci1 clock input/output receive data pin rxd input sci1 receive data input transmit data pin txd output sci1 transmit data output
203 12.1.4 register configuration table 12.2 summarizes the sci1 internal registers. these registers specify the data format and bit rate, and control the transmitter and receiver sections. table 12.2 registers name abbreviation r/w initial value address * 1 access size serial mode register smr1 r/w h'00 h'ffff81b0 8, 16 bit rate register brr1 r/w h'ff h'ffff81b1 8, 16 serial control register scr1 r/w h'00 h'ffff81b2 8, 16 transmit data register tdr1 r/w h'ff h'ffff81b3 8, 16 serial status register ssr1 r/(w) * 2 h'84 h'ffff81b4 8, 16 receive data register rdr1 r h'00 h'ffff81b5 8, 16 notes: 1. do not attempt to access empty addresses. 2. the only value that can be written is a 0 to clear the flags. 12.2 register descriptions 12.2.1 receive shift register (rsr1) the receive shift register (rsr1) receives serial data. data input at the rxd pin is loaded into the rsr1 in the order received, lsb (bit 0) first, converting the data to parallel form. when one byte has been received, it is automatically transferred to the rdr1. the cpu cannot read or write the rsr1 directly. bit: 7 6 5 4 3 2 1 0 r/w: 12.2.2 receive data register (rdr1) the receive data register (rdr1) stores serial receive data. the sci1 completes the reception of one byte of serial data by moving the received data from the receive shift register (rsr1) into the rdr1 for storage. the rsr1 is then ready to receive the next data. this double buffering allows the sci1 to receive data continuously. the cpu can read but not write the rdr1. the rdr is initialized to h'00 by a power-on reset or in standby mode.
204 bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r 12.2.3 transmit shift register (tsr1) the transmit shift register (tsr1) transmits serial data. the sci1 loads transmit data from the transmit data register (tdr1) into the tsr1, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci1 automatically loads the next transmit data from the tdr1 into the tsr1 and starts transmitting again. if the tdre bit of the ssr1 is 1, however, the sci1 does not load the tdr1 contents into the tsr1. the cpu cannot read or write the tsr1 directly. bit: 7 6 5 4 3 2 1 0 r/w: 12.2.4 transmit data register (tdr1) the transmit data register (tdr1) is an 8-bit register that stores data for serial transmission. when the sci1 detects that the transmit shift register (tsr1) is empty, it moves transmit data written in the tdr1 into the tsr1 and starts serial transmission. continuous serial transmission is possible by writing the next transmit data in the tdr1 during serial transmission from the tsr1. the cpu can always read and write the tdr1. the tdr1 is initialized to h'ff by a power-on reset or in standby mode. bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 12.2.5 serial mode register (smr1) the serial mode register (smr1) is an 8-bit register that specifies the sci1 serial communication format and selects the clock source for the baud rate generator.
205 the cpu can always read and write the smr1. the smr1 is initialized to h'00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 c/ a chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w ? bit 7?ommunication mode (c/ a ): sets the sci operation mode to either start-stop synchronous mode or clock synchronous mode. bit 7: c/ a description 0 start-stop synchronous mode (initial value) 1 clock synchronous mode ? bit 6?haracter length (chr): selects 7-bit or 8-bit data in the asynchronous mode. the number of data bits is fixed at eight in the clock synchronous mode, regardless of the chr setting. bit 6: chr description 0 eight-bit data (initial value) 1 seven-bit data when 7-bit data is selected, the msb (bit 7) of the transmit data register is not transmitted. ? bit 5?arity enable (pe): selects whether to add a parity bit to transmit data and to check the parity of receive data. a parity bit is added in the clock synchronous mode regardless of the setting of the pe bit, and no checking is performed. bit 5: pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. ? bit 4?arity mode (o/ e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only when the parity enable bit (pe) is set to 1 to enable parity addition and check. the o/ e setting is ignored when parity addition and check is disabled.
206 bit 4: o/ e description 0 even parity (initial value) if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 odd parity if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. ? bit 3?top bit length (stop): selects one or two bits as the stop bit length. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. bit 3: stop description 0 one stop bit (initial value) in transmitting, a single bit of 1 is added at the end of each transmitted character. 1 two stop bits in transmitting, two bits of 1 are added at the end of each transmitted character. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, is it treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next character to be transmitted. ? bit 2?ultiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, settings of the parity enable (pe) and parity mode (o/ e ) bits are ignored. also, the setting of the mp bit is valid only in the start-stop synchronous mode. the setting of the mp bit is ignored in the clock synchronous mode. for the multiprocessor communication function, see section 12.3.3, multiprocessor communication. bit 2: mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected ? bits 1 and 0?lock select 1 and 0 (cks1, cks0): these bits select the internal clock source of the on-chip baud rate generator. four clock sources are available; , /4, /16, or /64. for
207 further information on the clock source, bit rate register settings, and baud rate, see section 12.2.8, bit rate register. bit 1: cks1 bit 0: cks0 description 00 (initial value) 1 /4 10 /16 1 /64 12.2.6 serial control register (scr1) the serial control register (scr1) operates the sci1 transmitter/receiver, enables/disables interrupt requests. the cpu can always read and write the scr1. the scr1 is initialized to h'00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 tie rie te re mpie teie cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w ? bit 7?ransmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the transmit data register empty bit (tdre) in the serial status register (ssr1) is set to 1 by transfer of serial transmit data from the tdr1 to the tsr1. bit 7: tie description 0 transmit-data-empty interrupt request (txi) is disabled (initial value) the txi interrupt request can be cleared by reading tdre after it has been set to 1, then clearing tdre to 0, or by clearing tie to 0. 1 transmit-data-empty interrupt request (txi) is enabled ? bit 6?eceive interrupt enable (rie): enables or disables the receive-data-full interrupt (rxi) requested when the receive data register full bit (rdrf) in the serial status register (ssr1) is set to 1 by transfer of serial receive data from the rsr1 to the rdr1. it also enables or disables receive-error interrupt (eri) requests.
208 bit 6: rie description 0 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are disabled. (initial value) rxi and eri interrupt requests can be cleared by reading the rdrf flag or error flag (fer, per, or orer) after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. 1 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are enabled. ? bit 5?ransmit enable (te): enables or disables the sci1 serial transmitter. bit 5: te description 0 transmitter disabled (initial value) the transmit data register empty bit (tdre) in the serial status register (ssr1) is locked at 1. 1 transmitter enabled serial transmission starts when the transmit data register empty (tdre) bit in the serial status register (ssr1) is cleared to 0 after writing of transmit data into the tdr1. select the transmit format in the smr1 before setting te to 1. ? bit 4?eceive enable (re): enables or disables the sci1 serial receiver. bit 4: re description 0 receiver disabled (initial value) clearing re to 0 does not affect the receive flags (rdrf, fer, per, orer). these flags retain their previous values. 1 receiver enabled serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. select the receive format in the smr1 before setting re to 1. ? bit 3?ultiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie setting is used only if the multiprocessor mode bit (mp) in the serial mode register (smr1) is set to 1 during reception.
209 bit 3: mpie description 0 multiprocessor interrupts are disabled (normal receive operation) (initial value) mpie is cleared when the mpie bit is cleared to 0, or the multiprocessor bit (mpb) is set to 1 in receive data. 1 multiprocessor interrupts are enabled receive-data-full interrupt requests (rxi), receive-error interrupt requests (eri), and setting of the rdrf, fer, and orer status flags in the serial status register (ssr1) are disabled until data with the multiprocessor bit set to 1 is received. the sci does not transfer receive data from the rsr1 to the rdr1, does not detect receive errors, and does not set the rdrf, fer, and orer flags in the serial status register (ssr1). when it receives data that includes mpb = 1, mpb is set to 1, and the sci1 automatically clears mpie to 0, generates rxi and eri interrupts (if the tie and rie bits in the scr1 are set to 1), and allows the fer and orer bits to be set. ? bit 2?ransmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if tdr does not contain valid transmit data when the msb is transmitted. bit 2: teie description 0 transmit-end interrupt (tei) requests are disabled * (initial value) 1 transmit-end interrupt (tei) requests are enabled. * note: * the tei request can be cleared by reading the tdre bit in the serial status register (ssr1) after it has been set to 1, then clearing tdre to 0 and clearing the transmit end (tend) bit to 0; or by clearing the teie bit to 0. ? bits 1 and 0?lock enable 1 and 0 (cke1, cke0): these bits select the sci1 clock source and enable or disable clock output from the sck pin. depending on the combination of cke1 and cke0, the sck pin can be used for serial clock output, or serial clock input. select the sck pin function by using the pin function controller (pfc). the cke0 setting is valid only in the asynchronous mode, and only when the sci1 is internally clocked (cke1 = 0). the cke0 setting is ignored in the clock synchronous mode, or when an external clock source is selected (cke1 = 1). select the sci1 operating mode in the serial mode register (smr) before setting cke1 and cke0. for further details on selection of the sci1 clock source, see table 12.9 in section 12.3, operation.
210 bit 1: cke1 bit 0: cke0 description * 1 0 0 asynchronous mode internal clock, sck pin used for input pin (input signal is ignored) or output pin (output level is undefined) * 2 clock synchronous mode internal clock, sck pin used for synchronous clock output * 2 0 1 asynchronous mode internal clock, sck pin used for clock output * 3 clock synchronous mode internal clock, sck pin used for synchronous clock output 1 0 asynchronous mode external clock, sck pin used for clock input * 4 clock synchronous mode external clock, sck pin used for synchronous clock input 1 1 asynchronous mode external clock, sck pin used for clock input * 4 clock synchronous mode external clock, sck pin used for synchronous clock input notes: 1. the sck pin is multiplexed with other functions. use the pin function controller (pfc) to select the sck function for this pin, as well as the i/o direction. 2. initial value. 3. the output clock frequency is the same as the bit rate. 4. the input clock frequency is 16 times the bit rate. 12.2.7 serial status register (ssr1) the serial status register (ssr1) is an 8-bit register containing multiprocessor bit values, and status flags that indicate sci1 operating status. the cpu can always read and write the ssr1, but cannot write 1 in the status flags (tdre, rdrf, orer, per, and fer). these flags can be cleared to 0 only if they have first been read (after being set to 1). bits 2 (tend) and 1 (mpb) are read-only bits that cannot be written. the ssr1 is initialized to h'84 by a power-on reset or in standby mode. bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer per tend mpb mpbt initial value: 1 0 0 0 0 1 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * the only value that can be written is a 0 to clear the flag. ? bit 7?ransmit data register empty (tdre): indicates that the sci1 has loaded transmit data from the tdr1 into the tsr1 and new serial transmit data can be written in the tdr1.
211 bit 7: tdre description 0 tdr1 contains valid transmit data tdre is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 in tdre. 1 tdr1 does not contain valid transmit data (initial value) tdre is set to 1 when the chip is power-on reset or in standby mode, the te bit in the serial control register (scr1) is cleared to 0, or tdr1 contents are loaded into tsr1, so new data can be written in tdr1. ? bit 6?eceive data register full (rdrf): indicates that rdr1 contains received data. bit 6: rdrf description 0 rdr1 does not contain valid received data (initial value) rdrf is cleared to 0 when the chip is power-on reset or in standby mode, software reads rdrf after it has been set to 1, then writes 0 in rdrf. 1 rdr1 contains valid received data rdrf is set to 1 when serial data is received normally and transferred from rsr1 to rdr1. note: the rdr1 and rdrf are not affected by detection of receive errors or by clearing of the re bit to 0 in the serial control register (scr1). they retain their previous contents. if rdrf is still set to 1 when reception of the next data ends, an overrun error (orer) occurs and the received data is lost. ? bit 5?verrun error (orer): indicates that data reception ended abnormally due to an overrun error. bit 5: orer description 0 receiving is in progress or has ended normally (initial value) clearing the re bit to 0 in the serial control register (scr1) does not affect the orer bit, which retains its previous value. orer is cleared to 0 when the chip is power-on reset, in standby mode, or software reads orer after it has been set to 1, then writes 0 in orer. 1 a receive overrun error occurred rdr1 continues to hold the data received before the overrun error, so subsequent receive data is lost. serial receiving cannot continue while orer is set to 1. orer is set to 1 if reception of the next serial data ends when rdrf is set to 1.
212 ? bit 4?raming error (fer): indicates that data reception ended abnormally due to a framing error. bit 4: fer description 0 receiving is in progress or has ended normally (initial value) clearing the re bit to 0 in the serial control register (scr1) does not affect the fer bit, which retains its previous value. fer is cleared to 0 when the chip is power-on reset, in standby mode, or software reads fer after it has been set to 1, then writes 0 in fer. 1 a receive framing error occurred when the stop bit length is two bits, only the first bit is checked to see if it is a 1. the second stop bit is not checked. when a framing error occurs, the sci1 transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. fer is set to 1 if the stop bit at the end of receive data is checked and found to be 0. ? bit 3?arity error (per): indicates that data reception (with parity) ended abnormally due to a parity error. bit 3: per description 0 receiving is in progress or has ended normally (initial value) clearing the re bit to 0 in the serial control register (scr1) does not affect the per bit, which retains its previous value. per is cleared to 0 when the chip is power-on reset, in standby mode, or software reads per after it has been set to 1, then writes 0 in per. 1 a receive parity error occurred when a parity error occurs, the sci1 transfers the receive data into the rdr1 but does not set rdrf. serial receiving cannot continue while per is set to 1. per is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/ e ) in the serial mode register (smr1).
213 ? bit 2?ransmit end (tend): indicates that when the last bit of a serial character was transmitted, the tdr1 did not contain valid data, so transmission has ended. tend is a read- only bit and cannot be written. bit 2: tend description 0 transmission is in progress tend is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 in tdre. 1 end of transmission (initial value) tend is set to 1 when the chip is power-on reset or in standby mode, te is cleared to 0 in the serial control register (scr1), or tdre is 1 when the last bit of a one-byte serial character is transmitted. ? bit 1?ultiprocessor bit (mpb): stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving. the mpb is a read-only bit and cannot be written. bit 1: mpb description 0 multiprocessor bit value in receive data is 0 (initial value) if re is cleared to 0 when a multiprocessor format is selected, the mpb retains its previous value. 1 multiprocessor bit value in receive data is 1 ? bit 0?ultiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting. the setting of the mpbt bit is ignored in the clock synchronous mode, when the multiprocessor format is not being used, and when transmission is not taking place. bit 0: mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1
214 12.2.8 bit rate register (brr1) the bit rate register (brr1) is an 8-bit register that, together with the baud rate generator clock source selected by the cks1 and cks0 bits in the serial mode register (smr1), determines the serial transmit/receive bit rate. the cpu can always read and write the brr1. the brr1 is initialized to h'ff by a power-on reset. bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 12.3 lists examples of brr1 settings in the asynchronous mode. table 12.4 lists examples of brr1 settings in the clock synchronous mode. table 12.3 bit rates and brr1 settings (asynchronous mode) (mhz) bit rate 4 4.9152 6 (bits/s) n n error (%) n n error (%) n n error (%) 110 2 70 0.03 2 86 0.31 2 106 ?.44 150 1 207 0.16 1 255 0.00 2 77 0.16 300 1 103 0.16 1 127 0.00 1 155 0.16 600 0 207 0.16 0 255 0.00 1 77 0.16 1200 0 103 0.16 0 127 0.00 0 155 0.16 2400 0 51 0.16 0 63 0.00 0 77 0.16 4800 0 25 0.16 0 31 0.00 0 38 0.16 9600 0 12 0.16 0 15 0.00 0 19 ?.34 14400 0 8 ?.55 0 10 ?.03 0 12 0.16 19200 0 6 ?.99 0 7 0.00 0 9 ?.34 28800 0 3 8.51 0 4 6.67 0 6 ?.99 31250 0 3 0.00 0 4 ?.70 0 5 0.00 38400 0 2 8.51 0 3 0.00 0 4 ?.34
215 table 12.3 bit rates and brr1 settings (asynchronous mode) (cont) (mhz) bit rate 7.3728 8 9.8304 (bits/s) n n error (%) n n error (%) n n error (%) 110 2 130 ?.07 2 141 0.03 2 174 ?.26 150 2 95 0.00 2 103 0.16 2 127 0.00 300 1 191 0.00 1 207 0.16 1 255 0.00 600 1 95 0.00 1 103 0.16 1 127 0.00 1200 0 191 0.00 0 207 0.16 0 255 0.00 2400 0 95 0.00 0 103 0.16 0 127 0.00 4800 0 47 0.00 0 51 0.16 0 63 0.00 9600 0 23 0.00 0 25 0.16 0 31 0.00 14400 0 15 0.00 0 16 2.12 0 20 1.59 19200 0 11 0.00 0 12 0.16 0 15 0.00 28800 0 7 0.00 0 8 ?.55 0 10 ?.03 31250 0 6 5.33 0 7 0.00 0 9 ?.70 38400 0 5 0.00 0 6 ?.99 0 7 0.00
216 table 12.3 bit rates and brr1 settings (asynchronous mode) (cont) (mhz) bit rate 10 11.0592 12 (bits/s) n n error (%) n n error (%) n n error (%) 110 2 177 ?.25 2 195 0.19 2 212 0.03 150 2 129 0.16 2 143 0.00 2 155 0.16 300 2 64 0.16 2 71 0.00 2 77 0.16 600 1 129 0.16 1 143 0.00 1 155 0.16 1200 1 64 0.16 1 71 0.00 1 77 0.16 2400 0 129 0.16 0 143 0.00 0 155 0.16 4800 0 64 0.16 0 71 0.00 0 77 0.16 9600 0 32 ?.36 0 35 0.00 0 38 0.16 14400 0 21 ?.36 0 23 0.00 0 25 0.16 19200 0 15 1.73 0 17 0.00 0 19 ?.34 28800 0 10 ?.36 0 11 0.00 0 12 0.16 31250 0 9 0.00 0 10 0.54 0 11 0.00 38400 0 7 1.73 0 8 0.00 0 9 ?.34
217 table 12.3 bit rates and brr1 settings (asynchronous mode) (cont) (mhz) bit rate 12.288 14 14.7456 (bits/s) n n error (%) n n error (%) n n error (%) 110 2 217 0.08 2 248 ?.17 3 64 0.70 150 2 159 0.00 2 181 0.16 2 191 0.00 300 2 79 0.00 2 90 0.16 2 95 0.00 600 1 159 0.00 1 181 0.16 1 191 0.00 1200 1 79 0.00 1 90 0.16 1 95 0.00 2400 0 159 0.00 0 181 0.16 0 191 0.00 4800 0 79 0.00 0 90 0.16 0 95 0.00 9600 0 39 0.00 0 45 ?.93 0 47 0.00 14400 0 26 ?.23 0 29 1.27 0 31 0.00 19200 0 19 0.00 0 22 ?.93 0 23 0.00 28800 0 12 2.56 0 14 1.27 0 15 0.00 31250 0 11 2.40 0 13 0.00 0 14 ?.70 38400 0 9 0.00 0 10 3.57 0 11 0.00
218 table 12.3 bit rates and brr1 settings (asynchronous mode) (cont) (mhz) bit rate 16 17.2032 18 (bits/s) n n error (%) n n error (%) n n error (%) 110 3 70 0.03 3 75 0.48 3 79 ?.12 150 2 207 0.16 2 223 0.00 2 233 0.16 300 2 103 0.16 2 111 0.00 2 116 0.16 600 1 207 0.16 1 223 0.00 1 233 0.16 1200 1 103 0.16 1 111 0.00 1 116 0.16 2400 0 207 0.16 0 223 0.00 0 233 0.16 4800 0 103 0.16 0 111 0.00 0 116 0.16 9600 0 51 0.16 0 55 0.00 0 58 ?.69 14400 0 34 ?.79 0 36 0.90 0 38 0.16 19200 0 25 0.16 0 27 0.00 0 28 1.02 28800 0 16 2.12 0 18 ?.75 0 19 ?.34 31250 0 15 0.00 0 16 1.20 0 17 0.00 38400 0 12 0.16 0 13 0.00 0 14 ?.34
219 table 12.3 bit rates and brr1 settings (asynchronous mode) (cont) (mhz) bit rate 18.432 19.6608 20 (bits/s) n n error (%) n n error (%) n n error (%) 110 3 81 ?.22 3 86 0.31 3 88 ?.25 150 2 239 0.00 2 255 0.00 3 64 0.16 300 2 119 0.00 2 127 0.00 2 129 0.16 600 1 239 0.00 1 255 0.00 2 64 0.16 1200 1 119 0.00 1 127 0.00 1 129 0.16 2400 0 239 0.00 0 255 0.00 1 64 0.16 4800 0 119 0.00 0 127 0.00 0 129 0.16 9600 0 59 0.00 0 63 0.00 0 64 0.16 14400 0 39 0.00 0 42 ?.78 0 42 0.94 19200 0 29 0.00 0 31 0.00 0 32 ?.36 28800 0 19 0.00 0 20 1.59 0 21 ?.36 31250 0 17 2.40 0 19 ?.70 0 19 0.00 38400 0 14 0.00 0 15 0.00 0 15 1.73
220 table 12.4 bit rates and brr settings in clocked synchronous mode (mhz) bit rate 4 8 10 12 (bits/s) n n n n n n n n 110 3 141 3 212 3 212 3 212 250 2 249 3 124 3 155 3 187 500 2 124 2 249 3 77 3 93 1k 1 249 2 124 2 155 2 187 2.5k 1 99 1 199 1 249 2 74 5k 0 199 1 99 1 124 1 149 10k 0 99 0 199 0 249 1 74 25k 0 39 0 79 0 99 0 119 50k 0 19 0 39 0 49 0 59 100k 0 9 0 19 0 24 0 29 250k 0 3 0 7 0 9 0 11 500k 0 1 0 3 0 4 0 5 1m 0 1 0 2 2.5m 0 0 * 00 * 5m
221 table 12.4 bit rates and brr settings in clocked synchronous mode (cont) (mhz) bit rate 16 20 (bits/s) n n n n 110 3 212 3 212 250 3 249 3 249 500 3 124 3 155 1k 2 249 3 77 2.5k 2 99 2 124 5k 1 199 1 249 10k 1 99 1 124 25k 0 159 0 199 50k 0 79 0 99 100k 0 39 0 49 250k 0 15 0 19 500k 0 7 0 9 1m 03 04 2.5m 0 1 5m 0 0 * note: settings with an error of 1% or less are recommended. legend blank: no setting available ? setting possible, but error occurs * : continuous transmission/reception is not possible.
222 the brr1 setting is calculated as follows: asynchronous mode: n = 10 6 1 64 2 2n 1 b clock synchronous mode: n = 10 6 1 8 2 2n 1 b b: bit rate (bit/s) n: baud rate generator brr1 setting (0 n 255) : operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the following table for the clock sources and value of n.) smr1 settings n clock source cks1 cks2 0 00 1 /4 0 1 2 /16 1 0 3 /64 1 1 the bit rate error in asynchronous mode is calculated as follows: error (%) = 1 100 (n + 1) b 64 2 2n 1 10 6 ? ? ? ? ? ?
223 table 12.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used for various frequencies. tables 12.6 and 12.7 show the maximum rates for external clock input.. table 12.5 maximum bit rates for various frequencies with baud rate generator (asynchronous mode) settings (mhz) maximum bit rate (bits/s) n n 4 125000 0 0 4.9152 153600 0 0 6 187500 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 11.0592 345600 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 18.432 576000 0 0 19.6608 614400 0 0 20 625000 0 0
224 table 12.6 maximum bit rates during external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (bits/s) 4 1.0000 62500 4.9152 1.2288 76800 6 1.5000 93750 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 11.0592 2.7648 172800 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 18.432 4.6080 288000 19.6608 4.9152 307200 20 5.0000 312500 table 12.7 maximum bit rates during external clock input (clock synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bits/s) 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3
225 12.3 operation 12.3.1 overview for serial communication, the sci1 has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. asynchronous/clock synchronous mode and the transmission format are selected in the serial mode register (smr1), as shown in table 12.8. the sci1 clock source is selected by the c/ a bit in the serial mode register (smr1) and the cke1 and cke0 bits in the serial control register (scr), as shown in table 12.9. asynchronous mode: ? data length is selectable: seven or eight bits. ? parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). these selections determine the transmit/receive format and character length. ? in receiving, it is possible to detect framing errors (fer), parity errors (per), overrun errors (orer), and the break state. ? an internal or external clock can be selected as the sci1 clock source. ? when an internal clock is selected, the sci1 operates using the on-chip baud rate generator clock, and can output a clock with a frequency matching the bit rate. ? when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) clock synchronous mode: ? the communication format has a fixed 8-bit data length. ? in receiving, it is possible to detect overrun errors (orer). ? an internal or external clock can be selected as the sci1 clock source. ? when an internal clock is selected, the sci1 operates using the on-chip baud rate generator clock, and outputs a synchronous clock signal to external devices. ? when an external clock is selected, the sci1 operates on the input synchronous clock. the on-chip baud rate generator is not used.
226 table 12.8 smr1 settings and sci1 communication formats smr settings sci1 communication format mode bit 7 c/ a bit 6 chr bit 5 pe bit 2 mp bit 3 stop data length parity bit multipro- cessor bit stop bit length asynchronous 0 0000 8-bit not set not set 1 bit 1 2 bits 1 0 set 1 bit 1 2 bits 1 0 0 7-bit not set 1 bit 1 2 bits 1 0 set 1 bit 1 2 bits asynchronous 0 * 1 0 8-bit not set set 1 bit (multiprocessor * 1 2 bits format) 1 * 0 7-bit 1 bit * 1 2 bits clock synchronous 1 **** 8-bit not set none note: asterisks ( * ) in the table indicate don t-care bits. table 12.9 smr1 and scr1 settings and sci1 clock source selection smr1 scr1 settings sci1 transmit/receive clock mode bit 7 c/ a bit 1 cke1 bit 0 cke0 clock source sck pin function * asynchronous 0 0 0 internal sci1 does not use the sck pin 1 outputs a clock with frequency matching the bit rate 1 0 external inputs a clock with frequency 16 times the bit rate 1 clock synch- 1 0 0 internal outputs the synchronous clock ronous 1 1 0 external inputs the synchronous clock 1 note: * select the function in combination with the pin function controller (pfc).
227 12.3.2 operation in asynchronous mode in the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci1 are independent, so full duplex communication is possible. the transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 12.2 shows the general format of asynchronous serial communication. in asynchronous serial communication, the communication line is normally held in the marking (high) state. the sci1 monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and stop bit (high), in that order. when receiving in the asynchronous mode, the sci1 synchronizes on the falling edge of the start bit. the sci1 samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. 0 d0d1d2d3d4d5d6d7 1 1 0/1 1 1 (lsb) (msb) serial data start bit 1 bit transmit/receive data 7 or 8 bits one unit of communication data (characters or frames) idling (marking state) parity bit stop bit 1 or no bit 1 or 2 bits figure 12.2 data format in asynchronous communication (example: 8-bit data with parity and two stop bits)
228 transmit/receive formats: table 12.10 shows the 12 communication formats that can be selected in the asynchronous mode. the format is selected by settings in the serial mode register (smr1). table 12.10 serial communication formats (asynchronous mode) smr1 bits serial transmit/receive format and frame length bit 6: chr bit 5: pe bit 2: mp bit 3: stop 1 2345678 9 10 11 12 0000 start 8-bit data stop 0001 start 8-bit data stop stop 0100 start 8-bit data p stop 0101 start 8-bit data p stop stop 1000 start 7-bit data stop 1001 start 7-bit data stop stop 1100 start 7-bit data p stop 1101 start 7-bit data p stop stop 0 1 0 start 8-bit data mpb stop 0 1 1 start 8-bit data mpb stop stop 1 1 0 start 7-bit data mpb stop 1 1 1 start 7-bit data mpb stop stop : don t care bits. note: start: start bit stop: stop bit p: parity bit mpb: multiprocessor bit clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci1 transmit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (smr1) and bits cke1 and cke0 in the serial control register (scr1) (table 12.9).
229 when an external clock is input at the sck pin, it must have a frequency equal to 16 times the desired bit rate. when the sci1 operates on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as in figure 12.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 d0d1d2d3d4d5d6d70/1 1 1 1 frame figure 12.3 output clock and communication data phase relationship (asynchronous mode) sci1 initialization (asynchronous mode): before transmitting or receiving, clear the te and re bits to 0 in the serial control register (scr1), then initialize the sci1 as follows. when changing the operation mode or communication format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr1). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr1), which retain their previous contents. figure 12.4 is a sample flowchart for initializing the sci1. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. select the clock source in the serial control register (scr1). leave rie, tie, teie, mpie, te and re cleared to 0. 2. select the communication format in the serial mode register (smr1). 3. write the value corresponding to the bit rate in the bit rate register (brr1). 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr1) to 1. also set rie, tie, teie and mpie as necessary. setting te or re enables the sci1 to use the txd or rxd pin. the initial states are the marking transmit state, and the idle receive state (waiting for a start bit).
230 initialize clear te and re bits to 0 in scr1 set cke1 and cke0 bits in scr1 (te and re bits are 0) select transmit/receive format in smr1 set value to brr1 wait set te or re to 1 in scr1; set rie, tie, teie, and mpie as necessary 1-bit interval elapsed? end (1) (2) (3) (4) no yes figure 12.4 sample flowchart for sci1 initialization transmitting serial data (asynchronous mode): figure 12.5 shows a sample flowchart for transmitting serial data. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. sci1 initialization: set the txd pin using the pfc. 2. sci1 status check and transmit data write: read the serial status register (ssr1), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr1) and clear tdre to 0. 3. continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in tdr1, then clear tdre to 0. 4. to output a break at the end of serial transmission, first clear the port data register (dr) to 0, then clear the te to 0 in scr1 and use the pfc to establish the txd pin as an output port.
231 start transmitting initialize read tdre bit in ssr1 read tend bit in ssr1 clear te bit in scr1 to 0; select thetxd pin as an output port with the pfc tend = 1? end transmission (1) (2) (3) no yes tdre = 1? write transmission data to tdr1 and clear tdre bit in ssr1 to 0 all data transmitted? no yes output break signal? no yes set dr = 0 (4) yes no figure 12.5 sample flowchart for transmitting serial data
232 in transmitting serial data, the sci1 operates as follows: 1. the sci1 monitors the tdre bit in the ssr1. when tdre is cleared to 0, the sci1 recognizes that the transmit data register (tdr1) contains new data, and loads this data from the tdr1 into the transmit shift register (tsr1). 2. after loading the data from the tdr1 into the tsr1, the sci1 sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) is set to 1 in the scr1, the sci1 requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits of data are output, lsb first. c. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci1 checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci1 loads new data from the tdr1 into the tsr1, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci1 sets the tend bit to 1 in the ssr1, outputs the stop bit, then continues output of 1 bits (marking). if the transmit-end interrupt enable bit (teie) in the scr1 is set to 1, a transmit-end interrupt (tei) is requested. figure 12.6 shows an example of sci transmit operation in asynchronous mode.
233 01 1 1 0/1 0 1 tdre tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (marking state) txi interrupt request txi interrupt handler writes data in tdr and clears tdre to 0 tei interrupt request 1 frame d0 d1 d7 d0 d1 d7 0/1 txi interrupt request figure 12.6 sci1 transmit operation in asynchronous mode (8-bit data with parity and one stop bit) receiving serial data: figures 12.7 show a sample flowchart for receiving serial data. the procedure is as follows (the steps correspond to the numbers in the flowchart). 1. sci1 initialization: set the rxd pin using the pfc. 2. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer bits of the ssr1 to identify the error. after executing the necessary error handling, clear orer, per, and fer all to 0. receiving cannot resume if orer, per or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. 3. sci1 status check and receive-data read: read the serial status register (ssr1), check that rdrf is set to 1, then read receive data from the receive data register (rdr1) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 4. continue receiving serial data: read the rdr1 and rdrf bit and clear rdrf to 0 before the stop bit of the current frame is received.
234 start reception initialization read orer, per, and fer bits in ssr1 read reception data of rdr1 and clear rdrf bit in ssr1 to 0 end reception (4) no no yes yes read the rdrf bit in ssr1 rdrf = 1? per, fer, orer = 1? clear the re bit of scr1 to 0 yes no (3) (1) error handling (2) all data received? figure 12.7 sample flowchart for receiving serial data
235 start of error handling orer = 1? overrun error handling fer = 1? yes break? no framing error handling per = 1? yes parity error handling clear orer, per, and fer to 0 in ssr1 end clear re bit in scr1 to 0 no no no yes yes figure 12.7 sample flowchart for receiving serial data (cont)
236 in receiving, the sci1 operates as follows: 1. the sci1 monitors the communication line. when it detects a start bit (0), the sci1 synchronizes internally and starts receiving. 2. receive data is shifted into the rsr1 in order from the lsb to the msb. 3. the parity bit and stop bit are received. after receiving these bits, the sci1 makes the following checks: a. parity check. the number of 1s in the receive data must match the even or odd parity setting of the o/ e bit in the smr1. b. stop bit check. the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. c. status check. rdrf must be 0 so that receive data can be loaded from the rsr1 into the rdr1. if the data passes these checks, the sci1 sets rdrf to 1 and stores the received data in the rdr1. if one of the checks fails (receive error), the sci1 operates as indicated in table 12.11. note: when a receive error occurs, further receiving is disabled. while receiving, the rdrf bit is not set to 1, so be sure to clear the error flags. 4. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in the scr1, the sci1 requests a receive-data-full interrupt (rxi). if one of the error flags (orer, per, or fer) is set to 1 and the receive-data-full interrupt enable bit (rie) in the scr is also set to 1, the sci1 requests a receive-error interrupt (eri). figure 12.8 shows an example of sci1 receive operation in the asynchronous mode. table 12.11 receive error conditions and sci1 operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf is still set to 1 in ssr1 receive data not loaded from rsr1 into rdr1 framing error fer stop bit is 0 receive data loaded from rsr1 into rdr1 parity error per parity of receive data differs from even/odd parity setting in smr1 receive data loaded from rsr1 into rdr1
237 tdrf fer framing error generates eri interrupt request. 1 frame rxi interrupt handler reads data in rdr and clears rdrf to 0. 01 1 1 0/1 0 0 parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (marking state) d0 d1 d7 d0 d1 d7 0/1 rxi interrupt request figure 12.8 sci1 receive operation (8-bit data with parity and one stop bit) 12.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. the processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by a unique id. a serial communication cycle consists of an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. the receiving processor with a matching id continues to receive further incoming data. processors with ids not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 12.9 shows the example of communication among processors using the multiprocessor format.
238 communication formats: four formats are available. parity-bit settings are ignored when the multiprocessor format is selected. for details see table 12.8. clock: see the description in the asynchronous mode section. receiving processor a (id = 01) (id = 02) (id = 03) (id = 04) receiving processor b receiving processor c serial communication line h'01 h'aa (mpb = 0) (mpb = 1) id-transmit cycle: receiving processor address serial data mpb: multiprocessor bit transmitting processor receiving processor d data-transmit cycle: data sent to receiving processor specified by id figure 12.9 communication among processors using multiprocessor format (sending data h'aa to receiving processor a) transmitting multiprocessor serial data: figure 12.10 shows a sample flowchart for transmitting multiprocessor serial data. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. sci1 initialization: set the txd pin using the pfc. 2. sci1 status check and transmit data write: read the serial status register (ssr1), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr1). also set mpbt (multiprocessor bit transfer) to 0 or 1 in ssr1. finally, clear tdre to 0. 3. continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in tdr1, then clear tdre to 0. 4. output a break at the end of serial transmission: set the data register (dr) of the port to 0, then clear te to 0 in scr1 and set the txd pin function as output port with the pfc.
239 tdre = 1? write transmit data in tdr1 and set mpbt in ssr1 all data transmitted? yes tend = 1? read tend bit in ssr1 output break signal? yes set dr = 0 clear te bit in scr1 to 0; select thetxd pin function as an output port with the pfc end transmission yes read tdre bit in ssr1 clear tdre bit to 0 initialization no no yes no no (1) (2) (3) (4) start transmission figure 12.10 sample flowchart for transmitting multiprocessor serial data
240 in transmitting serial data, the sci1 operates as follows: 1. the sci1 monitors the tdre bit in the ssr1. when tdre is cleared to 0 the sci1 recognizes that the transmit data register (tdr1) contains new data, and loads this data from the tdr1 into the transmit shift register (tsr1). 2. after loading the data from the tdr1 into the tsr1, the sci1 sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in the scr1 is set to 1, the sci1 requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits are output, lsb first. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci1 checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci1 loads data from the tdr1 into the tsr1, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci1 sets the tend bit in the ssr1 to 1, outputs the stop bit, then continues output of 1 bits in the marking state. if the transmit-end interrupt enable bit (teie) in the scr1 is set to 1, a transmit-end interrupt (tei) is requested at this time. figure 12.11 shows an example of sci1 receive operation in the multiprocessor format. tdre tend txi interrupt handler writes data in tdr1 and clears tdre to 0 txi interrupt request tei interrupt request 1 frame 01 1 1 0/1 0 1 multiprocessor bit multiprocessor bit serial data start bit data stop bit start bit data stop bit idle (marking state) d0 d1 d7 d0 d1 d7 0/1 txi interrupt request figure 12.11 sci1 multiprocessor transmit operation (8-bit data with multiprocessor bit and one stop bit)
241 receiving multiprocessor serial data: figure 12.12 shows a sample flowchart for receiving multiprocessor serial data. the procedure for receiving multiprocessor serial data is listed below. 1. sci1 initialization: set the rxd pin using the pfc. 2. id receive cycle: set the mpie bit in the serial control register (scr1) to 1. 3. sci1 status check and compare to id reception: read the serial status register (ssr1), check that rdrf is set to 1, then read data from the receive data register (rdr1) and compare with the processor? own id. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. 4. receive error handling and break detection: if a receive error occurs, read the orer and fer bits in ssr1 to identify the error. after executing the necessary error processing, clear both orer and fer to 0. receiving cannot resume if orer or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. 5. sci1 status check and data receiving: read ssr1, check that rdrf is set to 1, then read data from the receive data register (rdr1).
242 rdrf = 1? fer = 1? or orer =1? rdrf = 1? all data received? no end reception yes set mpie bit in scr1 to 1 read rdrf bit of ssr1 initialization clear re bit in scr1 to 0 yes no (2) (1) (3) read orer and fer bits of ssr1 fer = 1? or orer =1? read rdrf bit in ssr1 read receive data from rdr1 is id the station s id no read orer and fer bits in ssr1 read receive data from rdr1 no error processing no yes (5) (4) yes yes no yes start reception figure 12.12 sample flowchart for receiving multiprocessor serial data
243 orer = 1? break? yes framing error handling yes start error handling overrun error handling yes fer = 1? clear orer and fer bits in ssr1 to 0 end no no no clear re bit in scr1 to 0 figure 12.12 sample flowchart for receiving multiprocessor serial data (cont)
244 figures 12.13 show examples of sci1 receive operation using a multiprocessor format. rdrf mpie rdr1 value id1 rxi interrupt request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads data in rdr1 and clears rdrf to 0 not station s id, so mpie is set to 1 again no rxi interrupt, rdr1 maintains state 01 1 1 10 1 serial data start bit stop bit (a) id does not match (b) id matches start bit stop bit idling (marking) d0 d1 d7 d0 d1 d7 0 mpb mpb mpb data (id1) data (data 1) rdrf mpie rdr1 value id1 id2 01 1 1 10 1 mpb mpb serial data start bit data (id2) data (data 2) stop bit start bit stop bit idling (marking) d0 d1 d7 d0 d1 d7 0 rxi interrupt request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads data in rdr1 and clears rdrf to 0 station s id, so receiving continues, with data received by the rxi interrupt processing routine mpie bit is again set to 1 mpb data2 figure 12.13 sci1 receive operation (8-bit data with multiprocessor bit and one stop bit)
245 12.3.4 clock synchronous operation in the clock synchronous mode, the sci1 transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci1 transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock. the transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 12.14 shows the general format in clock synchronous serial communication. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb msb synchroni- zation clock serial data * * transfer direction one unit (character or frame) of communication data note: * high except in continuous transmitting or receiving. figure 12.14 data format in clock synchronous communication in clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. data are guaranteed valid at the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from the lsb (first) to the msb (last). after output of the msb, the communication line remains in the state of the msb. in the clock synchronous mode, the sci1 transmits or receives data by synchronizing with the falling edge of the synchronization clock. communication format: the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci1 transmit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (smr1) and bits cke1 and cke0 in the serial control register (scr1). see table 12.9. when the sci1 operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the sci1 is not transmitting or receiving, the clock signal remains in the high state.
246 note: an overrun error occurs only during the receive operation, and the sync clock is output until the re bit is cleared to 0. when you want to perform a receive operation in one- character units, select external clock for the clock source. sci1 initialization (clock synchronous mode): before transmitting or receiving, software must clear the te and re bits to 0 in the serial control register (scr1), then initialize the sci1 as follows. when changing the mode or communication format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr1). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr1), which retain their previous contents. figure 12.15 is a sample flowchart for initializing the sci1. 1. select the clock source in the serial control register (scr1). leave rie, tie, teie, mpie, te, and re cleared to 0. 2. select the communication format in the serial mode register (smr1). 3. write the value corresponding to the bit rate in the bit rate register (brr1) unless an external clock is used. 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr1) to 1. also set rie, tie, teie, and mpie. the txd, rxd pins becomes usable in response to the pfc corresponding bits and the te, re bit settings.
247 start of initialization clear te and re bits to 0 in scr1 1-bit interval elapsed? set te and re to 1 in scr1; set rie, tie, teie, and mpie bits yes no (1) set rie, tie, teie, mpie, cke1, and cke0 bits in scr (te and re are 0) end wait select transmit/receive format in smr1 set value in brr1 (2) (3) (4) figure 12.15 sample flowchart for sci initialization transmitting serial data (clock synchronous mode): figure 12.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. sci1 initialization: set the txd pin function with the pfc. 2. sci1 status check and transmit data write: read ssr1, check that the tdre flag is 1, then write transmit data in tdr1 and clear the tdre flag to 0. 3. to continue transmitting serial data: after checking that the tdre flag is 1, indicating that data can be written, write data in tdr1, then clear the tdre flag to 0. when the dmac or dtc is activated by a transmit-data-empty interrupt request (txi) to write data in tdr1, the tdre flag is checked and cleared automatically.
248 start transmitting read tdre flag in ssr1 tdre = 1? write transmit data in tdr1 and clear tdre flag to 0 in ssr1 all data transmitted? read tend flag in ssr1 yes no no no yes tend = 1? yes end clear te bit to 0 in scr1 initialize (2) (3) (1) figure 12.16 sample flowchart for serial transmitting
249 figure 12.17 shows an example of sci1 transmit operation. bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 synchroni- zation clock serial data transmit direction bit 7 txi interrupt handler writes data in tdr1 and clears tdre to 0 1 frame txi request txi request tdre tend lsb msb tei request figure 12.17 example of sci1 transmit operation sci1 serial transmission operates as follows. 1. the sci1 monitors the tdre bit in the ssr1. when tdre is cleared to 0 the sci1 recognizes that the transmit data register (tdr1) contains new data and loads this data from the tdr1 into the transmit shift register (tsr1). 2. after loading the data from the tdr1 into the tsr1, the sci1 sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in the scr1 is set to 1, the sci1 requests a transmit-data-empty interrupt (txi) at this time. if clock output mode is selected, the sci1 outputs eight synchronous clock pulses. if an external clock source is selected, the sci1 outputs data in synchronization with the input clock. data are output from the txd pin in order from the lsb (bit 0) to the msb (bit 7). 3. the sci1 checks the tdre bit when it outputs the msb (bit 7). if tdre is 0, the sci1 loads data from the tdr1 into the tsr1, then begins serial transmission of the next frame. if tdre is 1, the sci1 sets the tend bit in the ssr1 to 1, transmits the msb, then holds the transmit data pin (txd) in the msb state. if the transmit-end interrupt enable bit (teie) in the scr1 is set to 1, a transmit-end interrupt (tei) is requested at this time. 4. after the end of serial transmission, the sck pin is held in the high state.
250 receiving serial data (clock synchronous mode): figure 12.18 shows a sample flowchart for receiving serial data. when switching from the asynchronous mode to the clock synchronous mode, make sure that orer, per, and fer are cleared to 0. if per or fer is set to 1, the rdrf bit will not be set and both transmitting and receiving will be disabled. the procedure for receiving serial data is listed below: 1. sci1 initialization: set the rxd pin using the pfc. 2. receive error handling: if a receive error occurs, read the orer bit in ssr1 to identify the error. after executing the necessary error handling, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. 3. sci1 status check and receive data read: read the serial status register (ssr1), check that rdrf is set to 1, then read receive data from the receive data register (rdr1) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 4. continue receiving serial data: read rdr1, and clear rdrf to 0 before the frame msb (bit 7) of the current frame is received. if the dmac is started by a receive-data-full interrupt (rxi) to read rdr1, the rdrf bit is cleared automatically so this step is unnecessary.
251 start reception initialization read the orer bit of ssr1 all data received? end reception (1) no yes orer = 1? read receive data from rdr1 and clear rdrf bit of ssr1 to 0 rdrf = 1? yes yes no clear re bit of scr1 to 0 no read rdrf bit of ssr1 error processing (3) (4) (2) figure 12.18 sample flowchart for serial receiving
252 error handling end clear orer bit of ssr1 to 0 overrun error processing figure 12.18 sample flowchart for serial receiving (cont) figure 12.19 shows an example of the sci1 receive operation. bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 synchroni- zation clock serial data transfer direction bit 7 read data with rxi interrupt processing routine and clear rdrf bit to 0 1 frame rxi request rxi request eri interrupt request generated by overrun error rdrf orer figure 12.19 example of sci1 receive operation in receiving, the sci1 operates as follows: 1. the sci1 synchronizes with serial clock input or output and initializes internally. 2. receive data is shifted into the rsr1 in order from the lsb to the msb. after receiving the data, the sci1 checks that rdrf is 0 so that receive data can be loaded from the rsr1 into the rdr1. if this check passes, the sci1 sets rdrf to 1 and stores the received data in the rdr1. if the check does not pass (receive error), the sci1 operates as indicated in table 12.11 and no further transmission or reception is possible. if the error flag is set to 1, the rdrf bit is
253 not set to 1 during reception, even if the rdrf bit is 0 cleared. when restarting reception, be sure to clear the error flag. 3. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in the scr1, the sci1 requests a receive-data-full interrupt (rxi). if the orer bit is set to 1 and the receive-data-full interrupt enable bit (rie) in the scr1 is also set to 1, the sci1 requests a receive-error interrupt (eri). transmitting and receiving serial data simultaneously (clock synchronous mode): figure 12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. sci1 initialization: set the txd and rxd pins using the pfc. 2. sci1 status check and transmit data write: read the serial status register (ssr1), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr1) and clear tdre to 0. the txi interrupt can also be used to determine if the tdre bit has changed from 0 to 1. 3. receive error handling: if a receive error occurs, read the orer bit in ssr1 to identify the error. after executing the necessary error processing, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. 4. sci1 status check and receive data read: read the serial status register (ssr1), check that rdrf is set to 1, then read receive data from the receive data register (rdr1) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 5. continue transmitting and receiving serial data: read the rdrf bit and rdr1, and clear rdrf to 0 before the frame msb (bit 7) of the current frame is received. before the msb (bit 7) of the current frame is received, read the tdre bit and check that it is safe to write (if it reads 1); if so, write data in tdr1, then clear tdre to 0. note: in switching from transmitting or receiving to simultaneous transmitting and receiving, simultaneously clear the te bit and re bit to 0, then simultaneously set the te bit and re bit to 1.
254 start transmitting/receive initialization read tdre bit in ssr1 all data transmitted/and received end transmission/reception (1) (2) no yes tdre = 1? write transmission data in tdr1 and clear tdre bit of ssr1 to 0 rdrf = 1? yes no clear te and re bits of scr1 to 0 yes no read orer bit of ssr1 error handling (3) orer = 1? yes read receive data of rdr1, and clear rdrf bit of ssr1 to 0 read rdrf bit of ssr1 (4) (5) no figure 12.20 sample flowchart for serial transmission
255 12.4 interrupt the sci1 has four interrupt sources: transmit-end (tei), receive-error (eri), receive-data-full (rxi), and transmit-data-empty (txi). table 12.12 lists the interrupt sources and indicates their priority. these interrupts can be enabled and disabled by the tie, rie, and teie bits in the serial control register (scr1). each interrupt request is sent separately to the interrupt controller. txi is requested when the tdre bit in the serial status register (ssr1) is set to 1. rxi is requested when the rdrf bit in the ssr1 is set to 1. eri is requested when the orer, fer, or per bit in the ssr1 is set to 1. tei is requested when the tend bit in the ssr1 is set to 1. where the txi interrupt indicates that transmit data writing is enabled, the tei interrupt indicates that the transmit operation has ended. table 12.12 sci1 interrupt sources interrupt source description priority eri receive error (orer, per, or fer) high rxi receive data full (rdrf) txi transmit data empty (tdre) tei transmit end (tend) low
256 12.5 notes on use the following points should be noted when using the sci1. tdr1 write and tdre flags: the tdre bit in the serial status register (ssr1) is a status flag indicating loading of transmit data from tdr1 into tsr1. the sci1 sets tdre to 1 when it transfers data from tdr1 to tsr1. data can be written to tdr1 regardless of the tdre bit status. if new data is written in tdr1 when tdre is 0, however, the old data stored in tdr1 will be lost because the data has not yet been transferred to the tsr1. before writing transmit data to the tdr1, be sure to check that tdre is set to 1. simultaneous multiple receive errors: table 12.13 indicates the state of the ssr1 status flags when multiple receive errors occur simultaneously. when an overrun error occurs, the rsr1 contents cannot be transferred to the rdr1, so receive data is lost. table 12.13 ssr1 status flags and transfer of receive data ssr1 status flags receive data transfer receive error status rdrf orer fer per rsr1 rdr1 overrun error 1 1 0 0 x framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 x overrun error + parity error 1 1 0 1 x framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1111x note: o = receive data is transferred from rsr1 to rdr1. x = receive data is not transferred from rsr1 to rdr1. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state, the input from the rxd pin consists of all 0s, so fer is set and the parity error flag (per) may also be set. in the break state, the sci1 receiver continues to operate, so if the fer bit is cleared to 0, it will be set to 1 again. sending a break signal: the txd pin becomes a general i/o pin with the i/o direction and level determined by the i/o port data register (dr) and pin function controller (pfc) control register (cr). these conditions allow break signals to be sent. the dr value is substituted for the marking status until the pfc is set. consequently, the output port is set to initially output a 1. to send a break in serial transmission, first clear the dr to 0, then establish the txd pin as an output port
257 using the pfc. when te is cleared to 0, the transmission section is initialized regardless of the present transmission status. receive error flags and transmitter operation (clock synchronous mode only): when a receive error flag (orer, per, or fer) is set to 1, the sci will not start transmitting even if tdre is set to 1. be sure to clear the receive error flags to 0 before starting to transmit. note that clearing re to 0 does not clear the receive error flags. receive data sampling timing and receive margin in the asynchronous mode: the sci1 operates on a base clock of 16 times the bit rate frequency in the asynchronous mode. in receiving, the sci1 synchronizes internally with the falling edge of the start bit, which it samples on the base clock. receive data is latched on the rising edge of the eighth base clock pulse (figure 12.21). 078150781505 base clock receive data (rxd) synchronization sampling timing data sampling timing 8 clocks 16 clocks start bit 7.5 clocks +7.5 clocks d0 d1 figure 12.21 receive data sampling timing in the asynchronous mode the receive margin in the asynchronous mode can therefore be expressed as: m = (0.5 1 2n d 0.5 n ) (l 0.5) f (1 + f) 100% m : receive margin (%) n : ratio of clock frequency to bit rate (n = 16) d : clock duty cycle (d = 0 to 1.0) l : frame length (l = 9 to 12) f : absolute deviation of clock frequency from the equation above, if f = 0 and d = 0.5 the receive margin is 46.875%: d = 0.5, f = 0 m = (0.5 1/(2 16)) 100% = 46.875%
258 this is a theoretical value. a reasonable margin to allow in system designs is 20 to 30%. cautions for clock synchronous external clock mode ? set te = re = 1 only when the external clock sck is 1. ? do not set te = re = 1 until at least four clocks after the external clock sck has changed from 0 to 1. ? when receiving, rdrf is 1 when re is set to zero 2.5 to 3.5 clocks after the rising edge of the rxd d7 bit sck input, but it cannot be copied to rdr. caution for clock synchronous internal clock mode: when receiving, rdrf is 1 when re is set to zero 1.5 clocks after the rising edge of the rxd d7 bit sck output, but it cannot be copied to rdr. caution for sci register initialization in standby mode: the scr1, smr1, and brr1 registers incorporated into the serial communication interface (sci) of the SH7018f user chip are not initialized in standby mode. consequently, if a transition is made to standby mode while the tie bit in scr1 is set to 1, the tdre bit in the serial status register (ssr1) will be set to 1, and after recovery from standby mode a transmit-data-empty interrupt (txi) will be generated. when switching to standby mode, therefore, coding that initializes the scr1, smr1, and brr1 registers must be inserted immediately before the relevant sleep instruction.
259 section 13 a/d converter (a/d) 13.1 overview the a/d converter has 10-bit resolution, and can select from a maximum of eight channels of analog inputs. 13.1.1 features the a/d converter has the following features: ? 10-bit resolution ? eight input channels ? high-speed conversion ? minimum conversion time: 6.7 ? per channel (for 20-mhz operation) ? two operating modes: single mode or scan mode ? single mode: a/d conversion on one channel ? scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers conversion results transferred to and stored in data registers corresponding to each channel. ? sample and hold function ? a/d conversion end interrupt generation an a/d conversion end interrupt (adi) request can be generated on completion of a/d conversion. ? a/d conversion can be started by mtu trigger input.
260 13.1.2 block diagram figure 13.1 is the block diagram of the a/d converter. control circuit a/d converter comparator sample and hold circuit adcr: addcsr: addra: addrb: addrc: addrd: a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d 10-bit d/a module data bus internal data bus addra addrb addrc addrd + avcc avss an0 an1 an2 an3 an4 an5 an6 an7 adi interrupt signal mtu trigger /8 /16 bus interface analog multiplexer adcsr adcr successive approximations register figure 13.1 a/d converter block diagram
261 13.1.3 pin configuration table 13.1 shows the input pins used by the a/d converter. the seven analog input pins are divided into two groups: group 0, comprising analog input pins 0 to 3 (an0 to an3), and group 1, comprising analog input pins 4 to 7 (an4 to an7). the av cc and av ss pins are for the a/d converter internal analog section power supply. table 13.1 pin configuration pin abbreviation i/o function analog supply av cc i analog section power supply analog ground av ss i analog section ground and a/d conversion reference voltage analog input 0 an0 i analog input group 0 analog input 1 an1 i analog input 2 an2 i analog input 3 an3 i analog input 4 an4 i analog input group 1 analog input 5 an5 i analog input 6 an6 i analog input 7 an7 i
262 13.1.4 register configuration table 13.2 shows the configuration of the a/d converter registers. table 13.2 register configuration name abbreviation r/w initial value address access size a/d data register ah addrah r h?0 h'ffff8420 8,16 a/d data register al addral r h?0 h'ffff8421 16 a/d data register bh addrbh r h?0 h'ffff8422 8,16 a/d data register bl addrbl r h?0 h'ffff8423 16 a/d data register ch addrch r h?0 h'ffff8424 8,16 a/d data register cl addrcl r h?0 h'ffff8425 16 a/d data register dh addrdh r h?0 h'ffff8426 8,16 a/d data register dl addrdl r h?0 h'ffff8427 16 a/d control/status register adcsr r/(w) * h'00 h'ffff8428 8,16 a/d control register adcr r/w h'7f h'ffff8429 8,16 note: * only 0 can be written to bit 7 to clear the flag. 13.2 register descriptions 13.2.1 a/d data registers a to d (addra to addrd) the a/d data registers (addr) are 16-bit read-only registers for storing a/d conversion results. there are four of these registers, addra through addrd. the a/d-converted data is 10-bit data which is transferred to the addr for the selected channel for storage. the upper 8 bits of the converted data correspond to the upper byte of the addr, and the lower 2 bits correspond to the lower byte. bits 5 to 0 of the lower byte of the addr are reserved. these bits are always read as 0. the write value should always be 0. table 13.3 shows the correspondence between the analog input channels and the addr registers. the addr registers can be read by the cpu at all times. the upper byte is read directly, but the lower byte data is transferred via a temporary register (temp). for details, see section 13.3, cpu interface. the addr registers are initialized to h'0000 by a power-on reset.
263 bit: 15 14 13 12 11 10 9 8 addrn: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 addrn: ad1 ad0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r (n = a to d) table 13.3 correspondence between analog input channels and addra-addrd analog input channel group 0 group 1 a/d data register an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd 13.2.2 a/d control/status register (adcsr) the adcsr is an 8-bit read/write register used for a/d conversion operation control and to indicate status. the adcsr is initialized to h'00 by power-on reset. bit: 7 6 5 4 3 2 1 0 adf adie adst scan cks ch2 ch1 ch0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * the only value that can be written is a 0 to clear the flag.
264 ? bit 7?/d end flag (adf): this status flag indicates that a/d conversion has ended. bit 7: adf description 0 clear conditions (initial value) with adf = 1, by reading the adf flag then writing 0 in adf 1 set conditions ? single mode: when a/d conversion ends after conversion for all designated channels ? scan mode: after one round of a/d conversion for all specified channels ? bit 6?/d interrupt enable (adie): enables or disables interrupt requests (adi) after a/d conversion ends. bit 6: adie description 0 disables interrupt requests (adi) after a/d conversion ends (initial value) 1 enables interrupt requests (adi) after a/d conversion ends ? bit 5?/d start (adst): selects start or stop for a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by mtu trigger input. bit 5: adst description 0 a/d conversion halted (initial value) 1 single mode: start a/d conversion. automatically cleared to 0 after conversion for the designated channel ends. scan mode: start a/d conversion. continuous conversion until 0 cleared by software, and by power-on reset. ? bit 4?can mode (scan): selects single mode or scan mode for a/d conversion. for details of the operation in single mode and scan mode, see section 13.4, operation. change the mode only when adst = 0. bit 4: scan description 0 single mode (initial value) 1 scan mode
265 ? bit 3?lock select (cks): sets the a/d conversion time. change the conversion time only when adst = 0. bit 3: cks description 0 conversion time = 266 states (max.) (initial value) 1 conversion time = 134 states (max.) ? bits 2 to 0?hannel select 2 to 0 (ch2 to ch0): these bits, along with the scan bit, select the analog input channel. change the channel selection only when adst = 0. description bit 2: ch2 bit 1: ch1 bit 0: ch0 single mode scan mode 0 0 0 an0 (initial value) an0 (initial value) 0 0 1 an1 an0, an1 0 1 0 an2 an0 to an2 0 1 1 an3 an0 to an3 1 0 0 an4 an4 1 0 1 an5 an4, an5 1 1 0 an6 an4 to an6 1 1 1 an7 an4 to an7 13.2.3 a/d control register (adcr) the a/d control register (adcr) is an 8-bit read/write register that enables or disables starting of a/d conversion by mtu trigger input. the adcr is initialized to h'7f by a power-on reset. bit: 7 6 5 4 3 2 1 0 trge initial value: 0 1 1 1 1 1 1 1 r/w: r/w r r r r r r r
266 ? bit 7?rigger enable (trge): enables or disables starting of a/d conversion by mtu trigger input. bit 7: trge description 0 disables a/d conversion start by mtu trigger input (initial value) 1 a/d conversion is started by mtu trigger ? bits 6 to 0?eserved: these bits are always read as 1. the write value should always be 1. 13.3 cpu interface addra to addrd are 16-bit registers, but they are connected to the cpu by an 8-bit data bus. therefore, while the upper byte is accessed directly by the cpu, the lower byte is accessed via an 8-bit temporary register (temp). data is read from an addr register as follows. when the upper byte is read, the upper-byte value is transferred directly to the cpu and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading an addr register, always read the upper byte before the lower byte. this operation can be performed by reading addr from the upper byte address using a word transfer instruction (such as mov.w). it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 13.2 shows the data flow for access to an addr register.
267 upper-byte read cpu (h'aa) bus interface module data bus addrnh (h'aa) addrnl (h'40) temp (h'40) lower-byte read cpu (h'40) bus interface module data bus addrnh (h'aa) addrnl (h'40) (n = a to d) (n = a to d) temp (h'40) figure 13.2 addr access operation (reading h'aa40)
268 13.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode.. the operation in these two modes is described below. 13.4.1 single mode (scan = 0) single mode should be selected for a/d conversion on only one channel. a/d conversion starts when the adst bit in the a/d control/status register (adcsr) is set to 1 by software or mtu trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. when conversion ends, the adf bit in adcsr is set to 1. if the adie bit in adcsr is also 1, an adi interrupt is requested. to clear the adf bit, first read adf when set to 1, then write 0 in adf. to prevent incorrect operation, a/d conversion should be halted by clearing the adst bit to 0 before changing the mode or analog input channel. after the change is made, a/d conversion is restarted by setting the adst bit to 1 (the mode or channel change and setting of the adst bit can be carried out simultaneously). an example of the operation when analog input channel 1 (an1) is selected and a/d conversion is performed in single mode is described below. figure 13.3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt request is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred to addrb. at the same time adf is set to 1, adst is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt service routine is started. 5. the routine reads adf set to 1, then writes 0 in adf. 6. the routine reads and processes the conversion result (addrb). 7. execution of the a/d interrupt service routine ends. after this, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated.
269 adie adst adf channel 0 (an0) channel 1 (an1) channel 2 (an2) channel 3 (an3) addra addrb addrc addrd a/d conversion starts conversion standby conversion standby conversion standby conversion result read conversion result read conversion standby a/d conversion 1 a/d conversion 2 a/d conversion result 1 a/d conversion result 2 conversion standby conversion standby set * set * set * clear * clear * note: * vertical arrows ( ) indicate instructions executed by software. figure 13.3 example of a/d converter operation (single mode, channel 1 selected)
270 13.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit in the a/d control/status register (adcsr) is set to 1 by software or mtu trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0; an4 when ch1 = 1). when more than one channel has been selected, a/d conversion starts on the second channel (an1 or an5) as soon as conversion ends on the first channel. a/d conversion is performed repeatedly on all the selected channels until the adst bit is cleared to 0. the conversion results are transferred to and stored in the addr register for each channel. to prevent incorrect operation, a/d conversion should be halted by clearing the adst bit to 0 before changing the mode or analog input channels. after the change is made, the first channel is selected and a/d conversion is restarted by setting the adst bit to 1 (the mode or channel change and setting of the adst bit can be carried out simultaneously). an example of the a/d conversion operation in scan mode when three channels (an0 to an2) in group 0 are selected is described below. figure 13.4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), group 0 is selected as the scan group (ch2 = 0), analog input channels an0-an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. a/d conversion starts on the first channel (an0), and when completed, the result is transferred to addra. next, conversion of the second channel (an1) starts automatically. 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion is completed for all the selected channels (an0 to an2), adf is set to 1, the first channel (an0) is selected again, and conversion is performed on that channel. if the adie bit is also 1, an adi interrupt is requested when conversion is completed. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after this, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0).
271 adst adf conversion standby conversion standby conversion standby a/d conversion 1 conversion standby conversion standby a/d conversion result 4 a/d conversion result 2 a/d conversion result 3 transfer hannel 0 (an0) hannel 1 (an1) hannel 2 (an2) hannel 3 (an3) addra addrb addrc addrd set * 1 clear * 1 clear * 1 a/d conversion time a/d conversion 2 a/d conversion 5 * 2 conversion standby conversion standby a/d conversion 3 continuous a/d conversion notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. conversion standby a/d conversion 4 a/d conversion result 1 figure 13.4 example of a/d converter operation (scan mode, channels an0 to an2 selected)
272 13.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample and hold circuit. the a/d converter samples the analog input at time t d after the adst bit is set to 1 in the a/d control/status register (adcsr), then starts conversion. figure 13.5 shows the a/d conversion timing, and table 13.4 shows a/d conversion times. as shown in figure 13.5, a/d conversion time tconv consists of a/d conversion start delay time t d and analog input sampling time t spl . the length of td is not fixed, but is determined by the timing of the write to adscr. the total conversion time therefore varies within the ranges shown in table 13.4. in scan mode, the t conv values given in table 13.4 apply to the first conversion. in the second and subsequent conversions, t conv is fixed at 256 states when cks = 0 or 128 states when cks = 1.
273 (1) (2) ck adf address write signal input sampling timing t d t spl t conv (1): (2): t d : t spl : t conv : adcsr write cycle adcsr address a/d conversion start delay time input sampling time a/d conversion time figure 13.5 a/d conversion timing table 13.4 a/d conversion times (single mode) cks = 0 cks = 1 symbol min typ max min typ max a/d conversion start delay time t d 10 17 6 9 input sampling time t spl 64 32 a/d conversion time t ccnv 259 266 131 134 note: unit: states (t cyc )
274 13.4.4 mtu trigger input timing a/d conversion can also be started by mtu trigger input. when the trge bit is set to 1 in the a/d control register (adcr), input from the mtu functions as trigger input. when an mtu trigger is detected, the adst bit is set to 1 in the a/d control/status register (adst), and the a/d converter is started. other operations, for both single mode and scan mode, are the same as when the adst bit is set to 1 by software, . figure 13.6 shows the timing for mtu trigger input. a/d conversion ck mtu trigger signal adst figure 13.6 external trigger input timing 13.5 a/d conversion precision definitions the a/d converter converts analog values input from analog input channels to 10-bit digital values by comparing them with an analog reference voltage. in this operation, the absolute precision of the a/d conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error. 1. offset error 2. full-scale error 3. quantization error 4. nonlinearity error
275 the above four kinds of error are described below with reference to figure 13.7. for the sake of clarity, this figure shows 3-bit a/d conversion rather than 10-bit a/d conversion. offset error (see figure 13.7 (1)) is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic when the digital output value changes from the minimum value (zero voltage) of 0000000000 (000 in the figure) to 0000000001 (001 in the figure ). full-scale error (see figure 13.7 (2)) is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic when the digital output value changes from 1111111110 (110 in the figure) to the maximum value (full-scale voltage) of 111111111 (111 in the figure). quantization error is the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 13.7 (3)). nonlinearity error is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic from zero voltage to full-scale voltage (see figure 13.7 (4)). this does not include offset error, full-scale error, and quantization error. 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs 111 110 101 100 011 010 001 000 analog input voltage (3) quantization error (4) nonlinearity error (2) full-scale error ideal a/d conversion characteristic digital output fs: full-scale voltage fs actual a/d conversion characteristic (1) offset error ideal a/d conversion characteristic digital output analog input voltage figure 13.7 a/d conversion precision definitions
276 13.6 notes on use the following points should be noted when using the a/d converter. 13.6.1 analog voltage settings analog input voltage range: the voltage applied to analog input pins during a/d conversion should be in the range av ss ann av cc (n = 0 to 7). av cc and av ss input voltages: for the av cc and av ss input voltages, set av cc = 3.3 v 10%, and av ss = v ss . when the a/d converter is not used, set av cc = v cc and av ss = v ss . 13.6.2 handling of analog input pins to prevent damage from surges and other abnormal voltages at the analog input pins (an0 to an7), connect a protection circuit such as that shown in figure 13.8. this circuit also includes a cr filter function that suppresses error due to noise. the circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. figure 13.9 shows an equivalent circuit for the analog input pins, and table 13.5 summarizes the analog input pin specifications. SH7018 avcc an0 to an7 avss 100 ? * note: 0.1 f 10 f 0.01 f figure 13.8 example of analog input pin protection circuit
277 an0 to an7 1.0 k ? 20 pf 1 m ? analog multiplexer a/d converter note: values are reference values. figure 13.9 analog input pin equivalent circuit table 13.5 analog input pin specifications item min max unit analog input capacitance 20 pf permitted signal source impedance 3k ?
278
279 section 14 pin function controller (pfc) 14.1 overview the pin function controller (pfc) consists of registers for selecting multiplex pin functions and their input/output direction. table 14.1 shows the SH7018's multiplex pins. the functions of the multiplex pins are determined by the operating mode. table 14.2 and table 14.3 show the pin functions in each operating mode and the initial values. table 14.1 multiplex pins port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) pin no. a pa15 i/o (port) ck output (cpg) 75 a pa14 i/o (port) rd output (bsc) 33 a pa12 i/o (port) wrl output (bsc) 34 a pa11 i/o (port) cs1 output (bsc) 35 a pa10 i/o (port) cs0 output (bsc) 36 a pa9 i/o (port) irq3 (intc) 42 a pa8 i/o (port) irq2 (intc) 44 a pa7 i/o (port) cs3 output (bsc) 37 a pa6 i/o (port) cs2 output (bsc) 38 a pa5 i/o (port) sck i/o (sci) 47 a pa4 i/o (port) txd output (sci) 48 a pa3 i/o (port) rxd input (sci) 49 a pa2 i/o (port) irq0 input (intc) 50 a pa1 i/o (port) 40 a pa0 i/o (port) 41 b pb9 i/o (port) irq7 input (intc) a21 output (bsc) 31 b pb8 i/o (port) irq6 input (intc) a20 output (bsc) wait input (bsc) 46 b pb7 i/o (port) a19 output (bsc) 29 b pb6 i/o (port) a18 output (bsc) 28 b pb5 i/o (port) 27 b pb4 i/o (port) 26 b pb3 i/o (port) irq1 input (intc) 24 b pb2 i/o (port) 23
280 table 14.1 multiplex pins (cont) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) pin no. b pb1 i/o (port) a17 output (bsc) 21 b pb0 i/o (port) a16 output (bsc) 20 c pc15 i/o (port) a15 output (bsc) 19 c pc14 i/o (port) a14 output (bsc) 18 c pc13 i/o (port) a13 output (bsc) 17 c pc12 i/o (port) a12 output (bsc) 16 c pc11 i/o (port) a11 output (bsc) 14 c pc10 i/o (port) a10 output (bsc) 13 c pc9 i/o (port) a9 output (bsc) 12 c pc8 i/o (port) a8 output (bsc) 11 c pc7 i/o (port) a7 output (bsc) 10 c pc6 i/o (port) a6 output (bsc) 9 c pc5 i/o (port) a5 output (bsc) 7 c pc4 i/o (port) a4 output (bsc) 6 c pc3 i/o (port) a3 output (bsc) 5 c pc2 i/o (port) a2 output (bsc) 4 c pc1 i/o (port) a1 output (bsc) 3 c pc0 i/o (port) a0 output (bsc) 2 d pd7 i/o (port) d7 i/o (bsc) 53 d pd6 i/o (port) d6 i/o (bsc) 54 d pd5 i/o (port) d5 i/o (bsc) 56 d pd4 i/o (port) d4 i/o (bsc) 58 d pd3 i/o (port) d3 i/o (bsc) 59 d pd2 i/o (port) d2 i/o (bsc) 60 d pd1 i/o (port) d1 i/o (bsc) 61 d pd0 i/o (port) d0 i/o (bsc) 62 e pe14 i/o (port) 88 e pe13 i/o (port) 87 e pe12 i/o (port) 86 e pe11 i/o (port) 85 e pe10 i/o (port) 84
281 table 14.1 multiplex pins (cont) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) pin no. e pe9 i/o (port) 83 e pe8 i/o (port) 82 e pe7 i/o (port) tioc2b i/o (mtu) 81 e pe6 i/o (port) tioc2a i/o (mtu) 80 e pe5 i/o (port) tioc1b i/o (mtu) 78 e pe4 i/o (port) tioc1a i/o (mtu) 77 e pe2 i/o (port) tioc0c i/o (mtu) 64 e pe0 i/o (port) tioc0a i/o (mtu) 63 f pf7 input (port) an7 input (a/d) 98 f pf6 input (port) an6 input (a/d) 97 f pf5 input (port) an5 input (a/d) 95 f pf4 input (port) an4 input (a/d) 94 f pf3 input (port) an3 input (a/d) 93 f pf2 input (port) an2 input (a/d) 92 f pf1 input (port) an1 input (a/d) 91 f pf0 input (port) an0 input (a/d) 90
282 14.2 register configuration the pfc registers are listed in table 14.3. table 14.3 pfc registers name abbreviation r/w initial value address access size port a io register l paiorl r/w h'0000 h'ffff8386 h'ffff8387 8, 16, 32 port a control register l1 pacrl1 r/w h'4000 h'ffff838c h'ffff838d 8, 16, 32 port a control register l2 pacrl2 r/w h'0000 h'ffff838e h'ffff838f 8, 16, 32 port b io register pbior r/w h'0000 h'ffff8394 h'ffff8395 8, 16, 32 port b control register 1 pbcr1 r/w h'0000 h'ffff8398 h'ffff8399 8, 16, 32 port b control register 2 pbcr2 r/w h'0000 h'ffff839a h'ffff839b 8, 16, 32 port c io register pcior r/w h'0000 h'ffff8396 h'ffff8397 8, 16, 32 port c control register pccr r/w h'0000 h'ffff839c h'ffff839d 8, 16, 32 port d io register l pdiorl r/w h'0000 h'ffff83a6 h'ffff83a7 8, 16, 32 port d control register l pdcrl r/w h'0000 h'ffff83ac h'ffff83ad 8, 16, 32 port e io register peior r/w h'0000 h'ffff83b4 h'ffff83b5 8, 16, 32 port e control register 2 pecr2 r/w h'0000 h'ffff83ba h'ffff83bb 8, 16, 32
283 14.3 register descriptions 14.3.1 port a io register l (paiorl) port a io register l (paiorl) is a 16-bit readable/writable register that selects the input/output direction of the pins in port a. the bits of this register correspond to the various pins. paiorl is enabled when the port a pins function as general input/output (pa15 to pa0) or serial clock (sck) pins, and disabled otherwise. when the port a pins function as pa15 to pa0 or sck, a pin becomes an output when the corresponding bit in paiorl is set to 1, and an input when the bit is cleared to 0. paiorl is initialized to h'0000 by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases it retains its previous data. bit: 15 14 13 12 11 10 9 8 pa15ior pa14ior pa12ior pa11ior pa10ior pa9ior pa8ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pa7ior pa6ior pa5ior pa4ior pa3ior pa2ior pa1ior pa0ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 14.3.2 port a control registers l1 and l2 (pacrl1, pacrl2) port a control registers l1 and l2 (pacrl1, pacrl2) are 16-bit readable/writable registers that select the functions of the pins in port a. pacrl1 is initialized to h'4000 by an external power-on reset. pacrl2 is initialized to h'0000 by an external power-on reset. however, they are not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases they retain their previous data.
284 port a control register l1 (pacrl1) bit: 15 14 13 12 11 10 9 8 pa15md pa14md pa12md initial value: 0 1 0 0 0 0 0 0 r/w: r r/w r r/w r r r r/w bit: 7 6 5 4 3 2 1 0 pa11md0 pa10md pa9md1 pa8md1 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r r/w r/w r r/w r bit 15?eserved: this bit is always read as 0. the write value should always be 0. bit 14?a15 mode (pa15md): selects the function of the pa15/ck pin. bit 14: pa15md description 0 general input/output (pa15) 1 clock output (ck) (initial value) bit 13?eserved: this bit is always read as 0. the write value should always be 0. bit 12?a14 mode (pa14md): selects the function of the pa14/ rd pin. bit 12: pa14md description 0 general input/output (pa14) (initial value) 1 read output ( rd ) bits 11 to 9?eserved: these bits are always read as 0. the write value should always be 0. bit 8?a12 mode (pa12md): selects the function of the pa12/ wrl pin. bit 8: pa12md description 0 general input/output (pa12) (initial value) 1 chip select output ( wrl ) bit 7?eserved: these bits are always read as 0. the write value should always be 0.
285 bit 6?a11 mode (pa11md): selects the function of the pa11/ cs1 pin. bit 6: pa11md description 0 general input/output (pa11) (initial value) 1 chip select output ( cs1 ) bit 5?eserved: this bit is always read as 0. the write value should always be 0. bit 4?a10 mode (pa10md): selects the function of the pa10/ cs0 pin. bit 4: pa10md description 0 general input/output (pa10) (initial value) 1 chip select output ( cs0 ) bit 3?a9 mode 1 (pa9md1): this bit selects the function of the pa9/ irq3 pin. bit 3: pa9md1 description 0 general input/output (pa9) (initial value) 1 interrupt request input ( irq3 ) bit 2?eserved: this bit is always read as 0. the write value should always be 0. bit 1?a8 mode 1 (pa8md1): this bit selects the function of the pa8/ irq2 pin. bit 1: pa8md1 description 0 general input/output (pa8) (initial value) 1 interrupt request input ( irq2 ) bit 0?eserved: this bit is always read as 0. the write value should always be 0.
286 port a control register l2 (pacrl2) bit: 15 14 13 12 11 10 9 8 pa7md1 pa6md1 pa5md0 pa4md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r/w r r r/w r r/w bit: 7 6 5 4 3 2 1 0 pa3md pa2md1 pa2md0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r r r r bit 15?a7 mode 1 (pa7md1): this bit selects the function of the pa7/ cs3 pin. bit 15: pa7md1 description 0 general input/output (pa7) (initial value) 1 chip select output ( cs3 ) bit 14?eserved: this bit is always read as 0. the write value should always be 0. bit 13?a6 mode 1 (pa6md1): this bit selects the function of the pa6/ cs2 pin. bit 13: pa6md1 description 0 general input/output (pa6) (initial value) 1 chip select output ( cs2 ) bit 12?eserved: this bit is always read as 0. the write value should always be 0. bit 10?a5 mode 0 (pa5md0): selects the function of the pa5/sck pin. bit 10: pa5md0 description 0 general input/output (pa5) (initial value) 1 serial clock input/output (sck1) bits 11 and 9?eserved: these bits are always read as 0. the write value should always be 0.
287 bit 8?a4 mode (pa4md): selects the function of the pa4/txd pin. bit 8: pa4md description 0 general input/output (pa4) (initial value) 1 transmit data output (txd) bit 7?eserved: this bit is always read as 0. the write value should always be 0. bit 6?a3 mode (pa3md): selects the function of the pa3/rxd pin. bit 6: pa3md description 0 general input/output (pa3) (initial value) 1 receive data input (rxd) bits 5 and 4?a2 mode 1 and 0 (pa2md1, pa2md0): these bits select the function of the pa2/ irq0 pin. bit 5: pa2md1 bit 4: pa2md0 description 0 0 general input/output (pa2) (initial value) 1 reserved 1 0 reserved 1 interrupt request input ( irq0 ) bits 3 to 0?eserved: these bits are always read as 0. the write value should always be 0.
288 14.3.3 port b io register (pbior) the port b io register (pbior) is a 16-bit readable/writable register that selects the input/output direction of the pins in port b. the bits of this register correspond to the various pins. pbior is enabled when the port b pins function as general input/output (pb9 to pb0) pins, and disabled otherwise. when the port b pins function as pb9 to pb0, a pin becomes an output when the corresponding bit in pbior is set to 1, and an input when the bit is cleared to 0. pbior is initialized to h'0000 by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases it retains its previous data. bit: 15 14 13 12 11 10 9 8 pb9ior pb8ior initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 pb7ior pb6ior pb5ior pb4ior pb3ior pb2ior pb1ior pb0ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 14.3.4 port b control registers 1 and 2 (pvcr1, pbcr2) port b control registers 1 and 2 (pvcr1, pbcr2) are 16-bit readable/writable registers that select the functions of the pins in port b. pvcr1 and pbcr2 are each initialized to h'0000 by an external power-on reset. however, they are not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases they retain their previous data.
289 port b control register 1 (pbcr1) bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 pb9md1 pb9md0 pb8md1 pb8md0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w bits 15 to 4?eserved: these bits are always read as 0. the write value should always be 0. bits 3 and 2?b9 mode 1 and 0 (pb9md1, pb9md0): these bits select the function of the pb9/ irq7 /a21 pin. bit 3: pb9md1 bit 2: pb9md0 description 0 0 general input/output (pb9) (initial value) 1 interrupt request input ( irq7 ) 1 0 address output (a21) 1 reserved bits 1 and 0?b8 mode 1 and 0 (pb8md1, pb8md0): these bits select the function of the pb8/ irq6 /a20/ wait pin. bit 1: pb8md1 bit 0: pb8md0 description 0 0 general input/output (pb8) (initial value) 1 interrupt request input ( irq6 ) 1 0 address output (a20) 1 wait state request input ( wait )
290 port b control register 2 (pbcr2) bit: 15 14 13 12 11 10 9 8 pb7md1 pb7md0 pb6md1 pb6md0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r r r bit: 7 6 5 4 3 2 1 0 pb3md0 pb1md pb0md initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r r r r/w r r/w bits 15 and 14?b7 mode 1 and 0 (pb7md1, pb7md0): these bits select the function of the pb7/a19 pin. bit 15: pb7md1 bit 14: pb7md0 description 0 0 general input/output (pb7) (initial value) 1 reserved 1 0 address output (a19) 1 reserved bits 13 and 12?b6 mode 1 and 0 (pb6md1, pb6md0): these bits select the function of the pb6/a18 pin. bit 13: pb6md1 bit 12: pb6md0 description 0 0 general input/output (pb6) (initial value) 1 reserved 1 0 address output (a18) 1 reserved bits 11 to 7?eserved: these bits are always read as 0. the write value should always be 0. bit 6?b3 mode 0 (pb3md0): selects the function of the pb3/ irq1 pin. bit 6: pb3md0 description 0 general input/output (pb3) (initial value) 1 interrupt request input ( irq1 ) bits 5 to 3?eserved: these bits are always read as 0. the write value should always be 0.
291 bit 2?b1 mode (pb1md): selects the function of the pb1/a17 pin. bit 2: pb1md description 0 general input/output (pb1) (initial value) 1 address output (a17) bit 1?eserved: this bit is always read as 0 and should only be written with 0. bit 0?b0 mode (pb0md): selects the function of the pb0/a16 pin. bit 0: pb0md description 0 general input/output (pb0) (initial value) 1 address output (a16) 14.3.5 port c io register (pcior) the port c io register (pcior) is a 16-bit readable/writable register that selects the input/output direction of the pins in port c. the bits of this register correspond to the various pins. pcior is enabled when the port c pins function as general input/output (pc15 to pc0) pins, and disabled otherwise. when the port c pins function as pc15 to pc0, a pin becomes an output when the corresponding bit in pcior is set to 1, and an input when the bit is cleared to 0. pcior is initialized to h'0000 by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases it retains its previous data. bit: 15 14 13 12 11 10 9 8 pc15ior pc14ior pc13ior pc12ior pc11ior pc10ior pc9ior pc8ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pc7ior pc6ior pc5ior pc4ior pc3ior pc2ior pc1ior pc0ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
292 14.3.6 port c control register (pccr) the port c control register (pccr) is a 16-bit readable/writable register that selects the functions of the pins in port c. pccr is initialized to h'0000 by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases they retain their previous data. bit: 15 14 13 12 11 10 9 8 pc15md pc14md pc13md pc12md pc11md pc10md pc9md pc8md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pc7md pc6md pc5md pc4md pc3md pc2md pc1md pc0md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 15?c15 mode (pc15md): selects the function of the pc15/a15 pin. bit 15: pc15md description 0 general input/output (pc15) (initial value) 1 address output (a15) bit 14?c14 mode (pc14md): selects the function of the pc14/a14 pin. bit 14: pc14md description 0 general input/output (pc14) (initial value) 1 address output (a14) bit 13?c13 mode (pc13md): selects the function of the pc13/a13 pin. bit 13: pc13md description 0 general input/output (pc13) (initial value) 1 address output (a13)
293 bit 12?c12 mode (pc12md): selects the function of the pc12/a12 pin. bit 12: pc12md description 0 general input/output (pc12) (initial value) 1 address output (a12) bit 11?c11 mode (pc11md): selects the function of the pc11/a11 pin. bit 11: pc11md description 0 general input/output (pc11) (initial value) 1 address output (a11) bit 10?c10 mode (pc10md): selects the function of the pc10/a10 pin. bit 10: pc10md description 0 general input/output (pc10) (initial value) 1 address output (a10) bit 9?c9 mode (pc9md): selects the function of the pc9/a9 pin. bit 9: pc9md description 0 general input/output (pc9) (initial value) 1 address output (a9) bit 8?c8 mode (pc8md): selects the function of the pc8/a8 pin. bit 8: pc8md description 0 general input/output (pc8) (initial value) 1 address output (a8) bit 7?c7 mode (pc7md): selects the function of the pc7/a7 pin. bit 7: pc7md description 0 general input/output (pc7) (initial value) 1 address output (a7)
294 bit 6?c6 mode (pc6md): selects the function of the pc6/a6 pin. bit 6: pc6md description 0 general input/output (pc6) (initial value) 1 address output (a6) bit 5?c5 mode (pc5md): selects the function of the pc5/a5 pin. bit 5: pc5md description 0 general input/output (pc5) (initial value) 1 address output (a5) bit 4?c4 mode (pc4md): selects the function of the pc4/a4 pin. bit 4: pc4md description 0 general input/output (pc4) (initial value) 1 address output (a4) bit 3?c3 mode (pc3md): selects the function of the pc3/a3 pin. bit 3: pc3md description 0 general input/output (pc3) (initial value) 1 address output (a3) bit 2?c2 mode (pc2md): selects the function of the pc2/a2 pin. bit 2: pc2md description 0 general input/output (pc2) (initial value) 1 address output (a2) bit 1?c1 mode (pc1md): selects the function of the pc1/a1 pin. bit 1: pc1md description 0 general input/output (pc1) (initial value) 1 address output (a1)
295 bit 0?c0 mode (pc0md): selects the function of the pc0/a0 pin. bit 0: pc0md description 0 general input/output (pc0) (initial value) 1 address output (a0) 14.3.7 port d io register l (pdiorl) port d io register l (pdiorl) is a 16-bit readable/writable register that selects the input/output direction of the pins in port d. the bits of this register correspond to the various pins. pdiorl is enabled when the port d pins function as general input/output (pd7 to pd0), and disabled otherwise. when the port d pins function as pd7 to pd0, a pin becomes an output when the corresponding bit in pdiorl is set to 1, and an input when the bit is cleared to 0. pdiorl is initialized to h'0000 by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases it retains its previous data. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 pd7ior pd6ior pd5ior pd4ior pd3ior pd2ior pd1ior pd0ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
296 14.3.8 port d control register l (pdcrl) port d control register l (pdcrl) is a 16-bit readable/writable register that selects the functions of the pins in port d. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 pd7md pd6md pd5md pd4md pd3md pd2md pd1md pd0md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w ? on-chip rom enabled extended mode port d pins function as both data i/o pins and general i/o pins. pdcrl settings are enabled. pdcrl is initialized to h'0000 by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases they retain their previous data. bits 15 to 8?eserved: these bits are always read as 0. the write value should always be 0. bit 7?d7 mode (pd7md): selects the function of the pd7/d7 pin. bit 7: pd7md description 0 general input/output (pd7) (initial value) 1 data input/output (d7) bit 6?d6 mode (pd6md): selects the function of the pd6/d6 pin. bit 6: pd6md description 0 general input/output (pd6) (initial value) 1 data input/output (d6) bit 5?d5 mode (pd5md): selects the function of the pd5/d5 pin. bit 5: pd5md description 0 general input/output (pd5) (initial value) 1 data input/output (d5)
297 bit 4?d4 mode (pd4md): selects the function of the pd4/d4 pin. bit 4: pd4md description 0 general input/output (pd4) (initial value) 1 data input/output (d4) bit 3?d3 mode (pd3md): selects the function of the pd3/d3 pin. bit 3: pd3md description 0 general input/output (pd3) (initial value) 1 data input/output (d3) bit 2?d2 mode (pd2md): selects the function of the pd2/d2 pin. bit 2: pd2md description 0 general input/output (pd2) (initial value) 1 data input/output (d2) bit 1?d1 mode (pd1md): selects the function of the pd1/d1 pin. bit 1: pd1md description 0 general input/output (pd1) (initial value) 1 data input/output (d1) bit 0?d0 mode (pd0md): selects the function of the pd0/d0 pin. bit 0: pd0md description 0 general input/output (pd0) (initial value) 1 data input/output (d0)
298 14.3.9 port e io register (peior) the port e io register (peior) is a 16-bit readable/writable register that selects the input/output direction of the pins in port e. the bits of this register correspond to the various pins. peior is enabled when the port e pins function as general input/output (pe14 to pe4, pe2, and pe0) pins or tioc pins for the mtu, and disabled otherwise. when the port e pins function as pe14 to pe4, pe2, and pe0 pins or tioc pins for the mtu, a pin becomes an output when the corresponding bit in peior is set to 1, and an input when the bit is cleared to 0. peior is initialized to h'0000 by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases it retains its previous data. bit: 15 14 13 12 11 10 9 8 pe14ior pe13ior pe12ior pe11ior pe10ior pe9ior pe8ior initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pe7ior pe6ior pe5ior pe4ior pe2ior pe0ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r/w r r/w
299 14.3.10 port e control register 2 (pecr2) port e control register 2 (pecr2) is a 16-bit readable/writable register that selects the functions of the pins in port e. pecr2 is initialized to h'0000 by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. in these cases it retains its previous data. bit: 15 14 13 12 11 10 9 8 pe7md pe6md pe5md pe4md initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r r/w r r/w r r/w bit: 7 6 5 4 3 2 1 0 pe2md0 pe0md0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r/w r r r r/w bit 15?eserved: this bit is always read as 0. the write value should always be 0. bit 14?e7 mode (pe7md): selects the function of the pe7/tioc2b pin. bit 14: pe7md description 0 general input/output (pe7) (initial value) 1 mtu input capture input/output compare output (tioc2b) bit 13?eserved: this bit is always read as 0. the write value should always be 0. bit 12?e6 mode (pe6md): selects the function of the pe6/tioc2a pin. bit 12: pe6md description 0 general input/output (pe6) (initial value) 1 mtu input capture input/output compare output (tioc2a) bit 11?eserved: this bit is always read as 0. the write value should always be 0.
300 bit 10?e5 mode (pe5md): selects the function of the pe5/tioc1b pin. bit 10: pe5md description 0 general input/output (pe5) (initial value) 1 mtu input capture input/output compare output (tioc1b) bit 9?eserved: this bit is always read as 0. the write value should always be 0. bit 8?e4 mode (pe4md): selects the function of the pe4/tioc1a pin. bit 8: pe4md description 0 general input/output (pe4) (initial value) 1 mtu input capture input/output compare output (tioc1a) bits 7 to 5?eserved: these bits are always read as 0. the write value should always be 0. bit 4?e2 mode 0 (pe2md0): selects the function of the pe2/tioc0c pin. bit 4: pe2md0 description 0 general input/output (pe2) (initial value) 1 mtu input capture input/output compare output (tioc0c) bits 3 to 1?eserved: these bits are always read as 0. the write value should always be 0. bit 0?e0 mode 0 (pe0md0): selects the function of the pe0/tioc0a pin. bit 0: pe0md0 description 0 general input/output (pe0) (initial value) 1 mtu input capture input/output compare output (tioc0a)
301 section 15 i/o ports (i/o) 15.1 overview all the port pins are multiplexed as general input/output pins (general input pins in the case of port f) and special function pins. the functions of the multiplex pins are selected by means of the pin function controller (pfc). each port is provided with a data register for storing the pin data. 15.2 port a port a is an input/output port with the 15 pins shown in figure 15.1. pa15 (i/o) / ck (output) port a pa14 (i/o) / rd (output) pa12 (i/o) / wrl (output) pa11 (i/o) / cs1 (output) pa10 (i/o) / cs0 (output) pa9 (i/o) / irq3 (input) pa8 (i/o) / irq2 (input) pa7 (i/o) / cs3 (input) pa6 (i/o) / cs2 (input) pa5 (i/o) / sck (i/o) pa4 (i/o) / txd (output) pa3 (i/o) / rxd (input) pa2 (i/o) / irq0 (input) pa1 (i/o) pa0 (i/o) figure 15.1 port a
302 15.2.1 register configuration the port a registers are shown in table 15.1. table 15.1 port a registers name abbreviation r/w initial value address access size port a data register l padrl r/w h'0000 h'ffff8382 h'ffff8383 8, 16, 32
303 15.2.2 port a data register l (padrl) port a data register l (padrl) is a 16-bit readable/writable register that stores port a data. the bits of this register correspond to the various pins. when a pin functions as a general output, if a value is written to padrl, that value is output directly from the pin, and if padrl is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if padrl is read the pin state, not the register value, is returned directly. if a value is written to padrl, that value is written to padrl but it does not affect the pin state. table 15.2 summarizes the port a data register read/write operations. padrl is initialized by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. bit: 15 14 13 12 11 10 9 8 pa15dr pa14dr pa12dr pa11dr pa10dr pa9dr pa8dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 15.2 port a data register (padr) read/write operations paior pin function read write 0 general input pin state value is written to padr, but does not affect pin state other than general input pin state value is written to padr, but does not affect pin state 1 general output padr value write value is output from pin other than general output padr value value is written to padr, but does not affect pin state
304 15.3 port b port a is an input/output port with the 10 pins shown in figure 15.2. pb9 (i/o) / irq7 (input) / a21 (output) port b pb8 (i/o) / irq6 (input) a20 (output) / wait (input) pb7 (i/o) / a19 (output) pb6 (i/o) / a18 (output) pb5 (i/o) pb4 (i/o) pb3 (i/o) / irq1 (input) pb2 (i/o) pb1 (i/o) / a17 (output) pb0 (i/o) / a16 (output) figure 15.2 port b 15.3.1 register configuration the port b registers are shown in table 15.3. table 15.3 port b registers name abbreviation r/w initial value address access size port b data register pbdr r/w h'0000 h'ffff8390 h'ffff8391 8, 16, 32
305 15.3.2 port b data register (pbdr) the port b data register (pbdr) is a 16-bit readable/writable register that stores port b data. the bits of this register correspond to the various pins. when a pin functions as a general output, if a value is written to pbdr, that value is output directly from the pin, and if pbdr is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pbdr is read the pin state, not the register value, is returned directly. if a value is written to pbdr, that value is written to pbdr but it does not affect the pin state. table 15.4 summarizes the port b data register read/write operations. padr is initialized by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. bit: 15 14 13 12 11 10 9 8 pb9dr pb8dr initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 15.4 port b data register (pbdr) read/write operations pbior pin function read write 0 general input pin state value is written to pbdr, but does not affect pin state other than general input pin state value is written to pbdr, but does not affect pin state 1 general output pbdr value write value is output from pin other than general output pbdr value value is written to pbdr, but does not affect pin state
306 15.4 port c port c is an input/output port with the 16 pins shown in figure 15.3. pc15 (i/o) port c /a15 (output) pc14 (i/o) /a14 (output) pc13 (i/o) /a13 (output) pc12 (i/o) /a12 (output) pc11 (i/o) /a11 (output) pc10 (i/o) /a10 (output) pc9 (i/o) /a9 (output) pc8 (i/o) /a8 (output) pc7 (i/o) /a7 (output) pc6 (i/o) /a6 (output) pc5 (i/o) /a5 (output) pc4 (i/o) /a4 (output) pc3 (i/o) /a3 (output) pc2 (i/o) /a2 (output) pc1 (i/o) /a1 (output) pc0 (i/o) /a0 (output) figure 15.3 port c 15.4.1 register configuration the port c registers are shown in table 15.5. table 15.5 port c registers name abbreviation r/w initial value address access size port c data register pcdr r/w h'0000 h'ffff8392 h'ffff8393 8, 16, 32
307 15.4.2 port c data register (pcdr) the port c data register (pcdr) is a 16-bit readable/writable register that stores port c data. the bits of this register correspond to the various pins. when a pin functions as a general output, if a value is written to pcdr, that value is output directly from the pin, and if pcdr is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pcdr is read the pin state, not the register value, is returned directly. if a value is written to pcdr, that value is written to pcdr but it does not affect the pin state. table 15.6 summarizes the port c data register read/write operations. pcdr is initialized by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. bit: 15 14 13 12 11 10 9 8 pc15dr pc14dr pc13dr pc12dr pc11dr pc10dr pc9dr pc8dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 15.6 port c data register (pcdr) read/write operations pcior pin function read write 0 general input pin state value is written to pcdr, but does not affect pin state other than general input pin state value is written to pcdr, but does not affect pin state 1 general output pcdr value write value is output from pin other than general output pcdr value value is written to pcdr, but does not affect pin state
308 15.5 port d port d is an input/output port with the eight pins shown in figure 15.4. pd7 (i/o) port d /d7 (i/o) pd6 (i/o)/d6 (i/o) pd5 (i/o)/d5 (i/o) pd4 (i/o)/d4 (i/o) pd3 (i/o)/d3 (i/o) pd2 (i/o)/d2 (i/o) pd1 (i/o)/d1 (i/o) pd0 (i/o)/d0 (i/o) figure 15.4 port d 15.5.1 register configuration the port d registers are shown in table 15.7. table 15.7 port d registers name abbreviation r/w initial value address access size port d data register l pddrl r/w h'0000 h'ffff83a2 h'ffff83a3 8, 16, 32
309 15.5.2 port d data register l (pddrl) port d data register l (pddrl) is a 16-bit readable/writable register that stores port d data. the bits of this register correspond to the various pins. when a pin functions as a general output, if a value is written to pddrl, that value is output directly from the pin, and if pddrl is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pddrl is read the pin state, not the register value, is returned directly. if a value is written to pddrl, that value is written to pddrl but it does not affect the pin state. table 15.8 summarizes the port d data register read/write operations. pddrl is initialized by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 15.8 port d data register (pddr) read/write operations pdior pin function read write 0 general input pin state value is written to pddr, but does not affect pin state other than general input pin state value is written to pddr, but does not affect pin state 1 general output pddr value write value is output from pin other than general output pddr value value is written to pddr, but does not affect pin state
310 15.6 port e port e is an input/output port with the 13 pins shown in figure 15.5. pe14 (i/o) port e pe13 (i/o) pe12 (i/o) pe11 (i/o) pe10 (i/o) pe9 (i/o) pe8 (i/o) pe7 (i/o) /tioc2b (i/o) pe6 (i/o) /tioc2a (i/o) pe5 (i/o) /tioc1b (i/o) pe4 (i/o) /tioc1a (i/o) pe2 (i/o) /tioc0c (i/o) pe0 (i/o) /tioc0a (i/o) figure 15.5 port e 15.6.1 register configuration the port e registers are shown in table 15.9. table 15.9 port e registers name abbreviation r/w initial value address access size port e data register pedr r/w h'0000 h'ffff83b0 h'ffff83b1 8, 16, 32
311 15.6.2 port e data register (pedr) the port e data register (pedr) is a 16-bit readable/writable register that stores port e data. the bits of this register correspond to the various pins. when a pin functions as a general output, if a value is written to pedr, that value is output directly from the pin, and if pedr is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pedr is read the pin state, not the register value, is returned directly. if a value is written to pedr, that value is written to pedr but it does not affect the pin state. table 15.10 summarizes the port e data register read/write operations. pedr is initialized by an external power-on reset. however, it is not initialized by a wdt reset, in standby mode, or in sleep mode. bit: 15 14 13 12 11 10 9 8 pe14dr pe13dr pe12dr pe11dr pe10dr pe9dr pe8dr initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pe7dr pe6dr pe5dr pe4dr pe2dr pe0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r/w r r/w table 15.10 port e data register (pedr) read/write operations peior pin function read write 0 general input pin state value is written to pedr, but does not affect pin state other than general input pin state value is written to pedr, but does not affect pin state 1 general output pedr value write value is output from pin other than general output pedr value value is written to pedr, but does not affect pin state
312 15.7 port f port f is an input port with the eight pins shown in figure 15.6. pf7 (input) port f /an7 (input) pf6 (input) /an6 (input) pf5 (input) /an5 (input) pf4 (input) /an4 (input) pf3 (input) /an3 (input) pf2 (input) /an2 (input) pf1 (input) /an1 (input) pf0 (input) /an0 (input) figure 15.6 port f 15.7.1 register configuration the port f registers are shown in table 15.11. table 15.11 port f registers name abbreviation r/w initial value address access size port f data register pfdr r/w depends on external pins h'ffff83b3 8
313 15.7.2 port e data register (pfdr) the port f data register (pfdr) is an 8-bit read-only register that stores port f data. the bits of this register correspond to the various pins. writes to these bits are ignored, and do not affect the pin states. when these bits are read the pin state, not the register value, is returned directly. however, 1 is returned while a/d converter analog input is being sampled. table 15.12 summarizes the port e data register read/write operations. pfdr is not initialized by a power-on reset, in standby mode, or in sleep mode. (the bits always reflect the pin states.) bit: 7 6 5 4 3 2 1 0 pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr initial value: ******** r/w: r r r r r r r r note: * these values depend on the pin state when the initial value is read. table 15.12 port f data register (pfdr) read/write operations pin function pin state read write input general input pin state is read ignored (does not affect pin state) ann 1 is read ignored (does not affect pin state) ann: analog input
314
315 section 16 160 kb flash memory (f-ztat) 16.1 features the SH7018 has 160 kbytes of on-chip flash memory. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. block erase (in single-block units) can be performed. erasing the entire memory requires erasure of each block in turn. block erasing can be performed as required on 4 kb, 32 kb, and 64 kb blocks. ? programming/erase times the flash memory programming time is 25 ms (typ.) for simultaneous 128-byte programming, equivalent to 195 ? (typ.) per byte, and the erase time is 10 ms (typ.). ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment with data transfer in boot mode, the SH7018? bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations. ? programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode.
316 16.2 overview 16.2.1 block diagram module bus bus interface/controller flash memory (160 kb) operating mode flmcr2 internal address bus internal data bus (32 bits) fwp pin mode pin ebr1 ebr2 flmcr1 ramer legend flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr1: erase block register 1 ebr2: erase block register 2 ramer: ram emulation register figure 16.1 block diagram of flash memory
317 16.2.2 mode transitions when the mode pins and the fwp pin are set in the reset state and a reset-start is executed, the SH7018 enters one of the operating modes shown in figure 16.2. in user mode, flash memory can be read but not programmed or erased. flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. boot mode on-board programming mode user program mode user mode reset state programmer mode res = 0 fwp = 0 fwp = 1 * 1 * 1 * 2 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. ram emulation possible 2. md0 = 1, md1 = 0, md2 = 1, md3 = 1 res = 0 md1 = 0, fwp = 0 res = 0 res = 0 md1 = 1, fwp = 1 md1 = 1, fwp = 0 figure 16.2 flash memory mode transitions
318 16.2.3 on-board programming modes boot mode figure 16.3 illustrates overwrite operation in the boot mode. for more information on the boot mode, see 16.6.1, boot mode. flash memory SH7018 ram host programming control program sci1 application program (old version) new application program flash memory SH7018 ram host sci1 application program (old version) boot program area new application program flash memory SH7018 ram host sci1 flash memory erase boot program new application program flash memory SH7018 program execution state ram host sci1 new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the SH7018 (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, entire flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. boot program boot program boot program area programming control program boot program area programming control program figure 16.3 overwrite operation in the boot mode
319 user program mode figure 16.4 illustrates overwrite operation in the user program mode. for more information on the user program mode, see 16.6.2, user program mode. flash memory SH7018 ram host programming/ erase control program sci1 boot program new application program flash memory SH7018 ram host sci1 new application program flash memory SH7018 ram host sci1 flash memory erase boot program new application program flash memory SH7018 program execution state ram host sci1 boot program boot program fwp assessment program application program (old version) new application program 1. initial state the fwp assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwp assessment program fwp assessment program transfer program transfer program fwp assessment program figure 16.4 example of overwrite operation in the user program mode
320 16.2.4 flash memory emulation in ram emulation should be performed in user mode or user program mode. when the emulation block set in ramer is accessed while the emulation function is being executed, data written in the overlap ram is read. ? user mode ? user program mode application program execution state flash memory emulation block ram sci1 overlap ram (emulation is performed on data written in ram) figure 16.5 ram emulation (ram overlap) when overlap ram data is confirmed, the rams bit is cleared, ram overlap is released, and writes should actually be performed to the flash memory. when the programming control program is transferred to ram, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten.
321 ? user program mode application program flash memory ram sci1 programming control program execution state overlap ram (programming data) programming data figure 16.6 ram emulation (flash memory overwrite) 16.2.5 differences between boot mode and user program mode boot mode user program mode entire memory erase yes yes block erase no yes programming control program * (2) (1) (2) (3) (1) erase/erase-verify (2) program/program-verify (3) emulation note: * to be provided by the user, in accordance with the recommended algorithm.
322 16.2.6 block configuration the flash memory is divided into eight 4 kb blocks, two 32 kb blocks, and one 64 kb block. the data in flash memory can be deleted one block at a time in the user program mode. address h'00000 address h'27fff 4 kb 4 kb 4 kb 4 kb 4 kb 4 kb 4 kb 4 kb 32 kb 32 kb 64 kb 160 kb figure 16.7 block configuration of area to be deleted 16.3 pin configuration the flash memory is controlled by means of the pins shown in table 16.1. table 16.1 flash memory pins pin name abbreviation i/o function power-on reset res input power-on reset flash memory write protect fwp input flash program/erase protection by hardware mode 3 md3 input sets SH7018 operating mode mode 2 md2 input sets SH7018 operating mode mode 1 md1 input sets SH7018 operating mode mode 0 md0 input sets SH7018 operating mode transmit data txd output serial transmit data output receive data rxd input serial receive data input
323 16.4 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 16.2. table 16.2 flash memory registers register name abbreviation r/w initial value address access size flash memory control register 1 flmcr1 r/w * 1 h'00 * 2 h'ffff8580 8 flash memory control register 2 flmcr2 r h'00 h'ffff8581 8 erase block register 1 ebr1 r/w * 1 h'00 * 3 h'ffff8582 8 erase block register 2 ebr2 r/w * 1 h'00 * 3 h'ffff8583 8 ram emulation register ramer r/w h'0000 h'ffff8628 8, 16, 32 notes: 1. writes are disabled when the fwe bit is set to 1 in flmcr1. 2. when a low level is input to the fwp pin, the initial value is h'80. 3. when a high level is input to the fwp pin, or if a low level is input and the swe bit in flmcr1 is not set, these registers are initialized to h'00. 4. flmcr1, flmcr2, ebr1, and ebr2 are 8-bit registers, and ramer is a 16-bit register. 5. only byte accesses are valid for flmcr1, flmcr2, ebr1, and ebr2, the access requiring 3 cycles. three cycles are required for a byte or word access to ramer, and 6 cycles for a longword access. 6. when a longword write is performed on ramer, 0 must always be written to the lower word (address h'ffff8630). operation is not guaranteed if any other value is written.
324 16.5 register descriptions 16.5.1 flash memory control register 1 (flmcr1) flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode is entered by setting swe to 1 when fwe = 1. program mode is entered by setting swe to 1 when fwe = 1, then setting the psu bit, and finally setting the p bit. erase mode is entered by setting swe to 1 when fwe = 1, then setting the esu bit, and finally setting the e bit. flmcr1 is initialized by a power-on reset, and in standby mode. its initial value is h'80 when a low level is input to the fwp pin, and h'00 when a high level is input. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes to bits swe, esu, psu, ev, and pv are enabled only when fwe = 1 and swe = 1; writes to the e bit only when fwe = 1, swe = 1, and esu = 1; and writes to the p bit only when fwe = 1, swe = 1, and psu = 1. bit: 7 6 5 4 3 2 1 0 fwe swe esu psu ev pv e p initial value: 1/0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w ? bit 7 flash write enable bit (fwe): sets hardware protection against flash memory programming/erasing. bit 7: fwe description 0 when a high level is input to the fwp pin (hardware-protected state) (initial value) 1 when a low level is input to the fwp pin ? bit 6 software write enable bit (swe): enables or disables the flash memory. this bit should be set before setting bits 5 to 0, ebr1 bits 7 to 0, and ebr2 bits 2 to 0. the flash memory cannot be read when swe is set to 1, except in the program verify/erase verify mode. bit 6: swe description 0 writes disabled (initial value) 1 writes enabled [setting condition] when fwe = 1
325 ? bit 5 erase setup bit (esu): prepares for a transition to erase mode. do not set the swe, psu, ev, pv, e, or p bit at the same time. bit 5: esu description 0 erase setup cleared (initial value) 1 erase setup [setting condition] when fwe = 1 and swe = 1 ? bit 4 program setup bit (psu): prepares for a transition to program mode. do not set the swe, esu, ev, pv, e, or p bit at the same time. bit 4: psu description 0 program setup cleared (initial value) 1 program setup [setting condition] when fwe = 1 and swe = 1 ? bit 3 erase-verify (ev): selects erase-verify mode transition or clearing. do not set the swe, esu, psu, pv, e, or p bit at the same time. bit 3: ev description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 ? bit 2 program-verify (pv): selects program-verify mode transition or clearing. do not set the swe, esu, psu, ev, e, or p bit at the same time. bit 2: pv description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when fwe = 1 and swe = 1
326 ? bit 1 erase (e): selects erase mode transition or clearing. do not set the swe, esu, psu, ev, pv, or p bit at the same time. bit 1: e description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu1 = 1 ? bit 0 program (p): selects program mode transition or clearing. do not set the swe, psu, esu, ev, pv, or e bit at the same time. bit 0: p description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when fwe = 1, swe = 1, and psu = 1
327 16.5.2 flash memory control register 2 (flmcr2) flmcr2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection). flmcr2 is initialized to h'00 by a power-on reset. when on-chip flash memory is disabled, a read will return h'00. bit: 7 6 5 4 3 2 1 0 fler initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r ? bit 7 flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. bit 7: fler description 0 flash memory is operating normally. flash memory program/erase protection (error protection) is disabled. [clearing condition] power-on reset (initial value) 1 an error has occurred during flash memory programming/erasing. flash memory program/erase protection (error protection) is enabled. [setting condition] see section 16.8.3, error protection. ? bits 6 to 0 reserved: these bits are always read as 0. the write value should always be 0.
328 16.5.3 erase block register 1 (ebr1) ebr1 is an 8-bit readable/writable register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a power-on reset, in standby mode, when a high level is input to the fwp pin, and when a low level is input to the fwp pin and the swe bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase- protected. as with ebr2, set only one bit of ebr1 (more than one bit cannot be set). if two or more bits are set, writes to the esu and e bits are invalid. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. the flash memory block configuration is shown in table 16.3. bit: 7 6 5 4 3 2 1 0 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 16.5.4 erase block register 2 (ebr2) ebr2 is an 8-bit register that specifies the flash memory erase area block by block. ebr2 is initialized to h'00 by a power-on reset and in standby mode, when a high level is input to the fwp pin, and when a low level is input to the fwp pin and the swe bit of flmcr1 is not set. when a bit in ebr2 is set to 1, the corresponding block can be erased. the other blocks are erase- protected. if the on-chip flash memory is disabled, a read will return h'00, and writes are invalid. the flash memory block configuration is shown in table 16.3. bit: 7 6 5 4 3 2 1 0 eb10 eb9 eb8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w ? bits 7 to 3 reserved: these bits are always read as 0. the write value should always be 0.
329 table 16.3 flash memory erase blocks block (size) address eb0 (4 kb) h'000000 to h'000fff eb1 (4 kb) h'001000 to h'001fff eb2 (4 kb) h'002000 to h'002fff eb3 (4 kb) h'003000 to h'003fff eb4 (4 kb) h'004000 to h'004fff eb5 (4 kb) h'005000 to h'005fff eb6 (4 kb) h'006000 to h'006fff eb7 (4 kb) h'007000 to h'007fff eb8 (32 kb) h'008000 to h'00ffff eb9 (64 kb) h'010000 to h'01ffff eb10 (32 kb) h'020000 to h'027fff 16.5.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer is initialized to h'0000 by a power-on reset. it is not initialized in standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are shown in table 16.4. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 rams ram1 ram0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w ? bits 15 to 3 reserved: these bits are always read as 0. the write value should always be 0.
330 ? bit 2 ram select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory block are program/erase-protected. bit 2: rams description 0 emulation not selected program/erase-protection of all flash memory blocks is disabled (initial value) 1 emulation selected program/erase-protection of all flash memory blocks is enabled ? bits 1 and 0 flash memory area selection (ram1, ram0): these bits are used together with bit 2 to select the flash memory area to be overlapped with ram. for each block, only the first 1 kb of addresses can be overlapped. (see table 16.4.) table 16.4 flash memory area divisions addresses block name rams ram1 ram0 h'fff800 to h'fffbff ram area 1 kb 0 ** h'004000 to h'0043ff eb4 (1 kb) 1 0 0 h'005000 to h'0053ff eb5 (1 kb) 1 0 1 h'006000 to h'0063ff eb6 (1 kb) 1 1 0 h'007000 to h'0073ff eb7 (1 kb) 1 1 1 16.6 on-board programming modes when pins are set to on-board programming mode and a power-on reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 16.5. for a diagram of the transitions to the various flash memory modes, see figure 16.2. table 16.5 setting on-board programming modes mode fwp md3 md2 md1 md0 boot mode 00000 user program mode 00010
331 16.6.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the sci1 to be used is set to channel asynchronous mode. when a reset-start is executed after the SH7018 pins have been set to boot mode in the power-on reset state, the boot program built into the SH7018 is started and the programming control program prepared in the host is serially transmitted to the SH7018 via sci1 (rxd, txd). in the SH7018, the programming control program received via sci1 is written into the programming control program area in on-chip ram. after the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). the transferred programming control program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 16.8, and the boot mode execution procedure in figure 16.9. rxd txd sci1 SH7018 flash memory write data reception verify data transmission host on-chip ram figure 16.8 system configuration in boot mode
332 note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate SH7018 measures low period of h'00 data transmitted by host SH7018 calculates bit rate and sets value in bit rate register after bit rate adjustment, SH7018 transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, SH7018 transmits one h'aa data byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte SH7018 transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits programming control program sequentially in byte units SH7018 transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, SH7018 transmits one h'aa data byte to host execute programming control program transferred to on-chip ram n + 1 n figure 16.9 boot mode execution procedure
333 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period (1 or more bits) when boot mode is initiated, the SH7018 measures the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. the SH7018 calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the SH7018. if reception cannot be performed normally, initiate boot mode again (power-on reset), and repeat the above operations. depending on the host s transmission bit rate and the SH7018 s system clock frequency, there will be a discrepancy between the bit rates of the host and the SH7018. to ensure correct sci operation, the host s transfer bit rate should be set to 4800bps, 9600bps. table 16.6 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the SH7018 bit rate is possible. the boot program should be executed within this system clock range. table 16.6 system clock frequencies for which automatic adjustment of SH7018 bit rate is possible host bit rate system clock frequency for which automatic adjustment of SH7018 bit rate is possible 19200 bps 16 to 20 mhz 9600 bps 8 to 20 mhz 4800 bps 4 to 20 mhz
334 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the programming control program is transferred via the sci, as shown in figure 16.10. the boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. h'fffff000 h'fffff800 h'ffffffff programming control program area (2 kbytes) boot program area (2 kbytes) figure 16.10 ram areas in boot mode note: the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note also that the boot program remains in this area of the on-chip ram even after control branches to the programming control program.
335 16.6.2 user program mode after setting fwp, the user should branch to, and execute, the previously prepared programming/erase control program. as the flash memory itself cannot be read while flash memory programming/erasing is being executed, the control program that performs programming and erasing should be run in on-chip ram or external memory. use the following procedure (figure 16.11) to execute the programming control program that writes to flash memory (when transferred to ram). execute user application program execute programming/ erase control program in ram (flash memory rewriting) transfer programming/erase control program to ram fwp = 0 (user program mode) write fwp assessment program and transfer program 1 2 3 4 5 figure 16.11 user program mode execution procedure note: when programming and erasing, start the watchdog timer so that measures can be taken to prevent program runaway, etc. memory cells may not operate normally if overprogrammed or overerased due to program runaway.
336 16.7 programming/erasing flash memory a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes can be made by setting the psu, esu, p, e, pv, and ev bits in flmcr1. the flash memory cannot be read while being programmed or erased. therefore, the program (programming control program) that controls flash memory programming/erasing should be located and executed in on-chip ram or external memory. notes: 1. operation is not guaranteed if setting/resetting of the swe, esu, psu, ev, pv, e, and p bits in flmcr1 is executed by a program in flash memory. 2. when programming or erasing, a low level is input to the fwp pin (programming/erasing will not be executed if a high level is input to the fwp pin). 3. programming should be performed in the erased state. do not perform additional programming on previously programmed addresses. 16.7.1 program mode follow the procedure shown in the program/program-verify flowchart in figure 16.12 to write data or programs to flash memory. performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carried out 128 bytes at a time. following the elapse of 1 s or more after the swe bit is set to 1 in flash memory control register 1 (flmcr1), 128-byte program data is stored in the program address (the lower 8 bits of the first address written to must be h'00, or h'80). the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. after this, preparation for program mode (program setup) is carried out by setting the psu bit in flmcr1, and after the elapse of 50 s or more, the operating mode is switched to program mode by setting the p bit in flmcr1. the time during which the p bit is set is the flash memory programming time. for the write time, refer to the table accompanying the program/program- verify flowchart.
337 16.7.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of a given programming time, the programming mode is exited (the p bit in flmcr1 is cleared, then the psun bit is cleared at least 5 s later). the watchdog timer is cleared after the elapse of 5 s or more, and the operating mode is switched to program-verify mode by setting the pv bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of 4 s or more. when the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. wait at least 2 s after the dummy write before performing this read operation. next, the written data is compared with the verify data, and reprogram data is computed (see figure 16.12) and transferred to the reprogram data area. after 128 bytes of data have been verified, exit program verify mode, wait for at least 2 s, clear the swe bit in flmcr1, then wait for at least 100 s. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. however, ensure that the program/program-verify sequence is not repeated more than 1,000 times on the same bits.
338 start end of programming end sub set swe bit in flmcr1 wait 1 s n = 1 m = 0 sub-routine-call see note 6 for pulse width note 6: write pulse width start of programming sub-routine write pulse set psu bit in flmcr1 enable wdt set p bit in flmcr1 wait 50 s clear p bit in flmcr1 wait 10 s, 30 s, or 200 s clear psu bit in flmcr1 wait 5 s disable wdt wait 5 s write pulse application subroutine ng ng ng ng reprogram ok ok wait 4 s wait 2 s * 2 * 4 * 5 * 1 wait 2 s set pv bit in flmcr1 h'ff dummy write to verify address read verify data program data = verify data? transfer additional program data to additional program data storage area additional program data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 128-byte data verification completed? m = 0? increment address programming failure ok original data (d) 0 1 verify data (v) 0 1 0 1 comments write 128-byte data in reprogram data storage area in ram consecutively to flash memory write pulse 30 s or 200 s ram program data storage area (128 bytes) reprogram data storage area (128 bytes) store 128-byte program data in program data storage area and reprogram data storage area number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 . . . 998 999 1000 write time (z) ( sec) 30 30 30 30 30 30 200 200 200 200 200 200 200 . . . 200 200 200 reprogram data computation transfer reprogram data to reprogram data storage area * 4 * 3 6 n? ng ok write 128-byte data in additional program data storage area in ram consecutively to flash memory additional write pulse 10 s wait 100 s * 1 note: use a 10 s write pulse for additional programming. reprogram data computation chart additional program data storage area (128 kbytes) ok ok ng programming must be executed in the erased state. do not perform additional programming on addresses that have already been programmed. * 4 n n + 1 n 1000? clear swe bit in flmcr1 wait 100 s 6 n? notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 1 28-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 32-bit (longword) units. 3. even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programmi ng if they fail the subsequent verify operation. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additio nal program data must be provided in ram. the reprogram and additional program data contents are modified as programming proceeds. 5. the write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for the pulse widths. when writing of additiona l program data is executed, a 10 s write pulse should be applied. reprogram data x means reprogram data when the write pulse is applied. programming completed programming incomplete; reprogram still in erased state; no action reprogram data (x') 0 1 verify data (v) 0 1 0 1 additional program data (y) 0 1 1 1 comments additional program data computation chart additional programming executed additional programming not executed additional programming not executed additional programming not executed reprogram data (x) 1 0 1 1 figure 16.12 program/program-verify flowchart
339 sample 128-byte programming program: the wait time set values (number of loops) are for the case where f = 20 mhz. for other frequencies, the set value is given by {wait time (s) f (mhz) 4}. registers used r11 (input): program data storage address r12 (input): programming destination address r13 (output): ok (normal) or ng (error) r0 10, 14: work registers flmcr1 .equ h'80 ok .equ h'0 ng .equ h'1 wait_x .equ 5 ; 1 s wait_y .equ 250 ; 50 s wait_z1 .equ 150 ; 30 s (1st to 6th time) wait_z5 .equ 1000 ; 200 s (7th to 1000th time) wait_za .equ 50 ; 10 s (additional write) wait_a .equ 25 ; 5 s wait_b .equ 25 ; 5 s wait_c .equ 20 ; 4 s wait_d .equ 10 ; 2 s wait_e .equ 10 ; 2 s wait_f .equ 500 ; 100 s wdt_tcsr .equ h'ffff8610 wdt_1m .equ h'a57a sweset .equ h'40 ; b'01000000 psuset .equ h'50 ; b'01010000 pset .equ h'51 ; b'01010001 pclear .equ h'50 ; b'01010000 psuclear .equ h'40 ; b'01000000 pvset .equ h'44 ; b'01000100 pvclear .equ h'40 ; b'01000000 sweclear .equ h'00 ; b'00000000 maxverify .equ 1000 ; flashprogram .equ $ mov r11,r3 ; save program data to mov.l #rdatabuff,r0 ; work area
340 mov.l #adatabuff,r2 mov #32,r6 copy_loop1 .equ $ mov.l @r3+,r1 mov.l r1,@r0 mov.l r1,@r2 add #4,r0 add #4,r2 dt r6 bf copy_loop1 mov.l #h'ffff8500,r0 ; initialize gbr ldc r0,gbr ; mov.l #wait_x,r2 mov #sweset,r0 mov.b r0,@(flmcr1,gbr) ; set swe wait_1 dt r2 ; wait 1 s bf wait_1 ; mov #1,r14 ; initialize n (r14) to 1 program_loop .equ $ mov #0,r5 ; initialize m (r5) to 0 mov.l #128,r2 ; write 128-byte data consecutively mov.l #rdatabuff,r3 mov r12,r6 write_loop1 .equ $ mov.b @r3+,r1 mov.b r1,@r6 add #1,r6 dt r2 bf write_loop1 ; mov.l #wdt_tcsr,r0 ; enable wdt mov.l #wdt_1m,r1 ; 1.6 ms cycle mov.w r1,@r0 ; mov.l #wait_y,r2
341 mov #psuset,r0 ; set psu mov.b r0,@(flmcr1,gbr) wait_2 dt r2 ; wait 50 s bf wait_2 ; mov.l #wait_z1,r2 ; 1st to 6th time mov #6,r3 cmp/ge r14,r3 bt under7 mov.l #wait_z5,r2 ; 7th to 1000th time under7 mov #pset,r0 ; set p mov.b r0,@(flmcr1,gbr) wait_3 dt r2 ; wait 30 s or 200 s bf wait_3 ; mov.l #wait_a,r2 mov #pclear,r0 ; clear p mov.b r0,@(flmcr1,gbr) wait_4 dt r2 ; wait 5 s bf wait_4 ; mov.l #wait_b,r2 mov #psuclear,r0 ; clear psu mov.b r0,@(flmcr1,gbr) wait_5 dt r2 ; wait 5 s bf wait_5 ; mov.l #wdt_tcsr,r0 ; disable wdt mov.w #h'a55f,r1 mov.w r1,@r0 ; mov.l #wait_c,r2 mov #pvset,r0 ; set pv mov.b r0,@(flmcr1,gbr) wait_6 dt r2 ; wait 4 s bf wait_6 ;
342 mov.l #adatabuff,r9 mov.l #rdatabuff,r7 mov r11,r1 mov r12,r3 mov #32,r6 mov.l #h'ffffffff,r4 ; verifyloop .equ $ mov.l r4,@r3 ; write h'ff to verify address mov.l r4,@r9 ; additional program data ram (adatabuff) initialization mov.l #wait_d,r2 wait_7 dt r2 ; wait 2 s bf wait_7 ; mov.l @r3+,r2 ; read verify data mov.l @r1+,r0 ; read program data (source data) cmp/eq r2,r0 ; verify check bt verify_ok mov #1,r5 ; if verify ng, assign 1 to m ; verify_ok .equ $ mov #6,r8 ; 6 or more writes? cmp/ge r14,r8 bf no_adwrt mov.l @r7,r10 ; read reprogram data or r2,r10 ; additional program data operation mov.l r10,@r9 ; store in additional program data ram (adatabuff) ; no_adwrt .equ $ mov.l r4,@r7 ; reprogram data ram (rdatabuff) initialization not r2,r2 ; reprogram data computation or r2,r0 mov.l r0,@r7 ; store in reprogram data ram (rdatabuff) ; add #4,r7 add #4,r9 dt r6
343 bf verifyloop ; mov.l #wait_e,r2 mov #pvclear,r0 ; clear pv mov.b r0,@(flmcr1,gbr) wait_8 dt r2 ; wait 2 s bf wait_8 ; mov #6,r8 ; 6 or more writes? cmp/ge r14,r8 bf no_adwrt2 ; mov.l #128,r2 ; consecutively write 128-byte date to mov.l #adatabuff,r3 ; additional program data ram (adatabuff) mov r12,r6 write_loop2 .equ $ mov.b @r3+,r1 mov.b r1,@r6 add #1,r6 dt r2 bf write_loop2 ; mov.l #wdt_tcsr,r0 ; enable wdt mov.l #wdt_1m,r1 ; 1.6 ms cycle mov.w r1,@r0 ; mov.l #wait_y,r2 mov #psuset,r0 ; set psu mov.b r0,@(flmcr1,gbr) wait_9 dt r2 ; wait 50 s bf wait_9 ; mov.l #wait_za,r2 ; 10 s additional write mov #pset,r0 ; set p mov.b r0,@(flmcr1,gbr) wait_10 dt r2 ; wait 10 s bf wait_10
344 ; mov.l #wait_a,r2 mov #pclear,r0 ; clear p mov.b r0,@(flmcr1,gbr) wait_11 dt r2 ; wait 5 s bf wait_11 ; mov.l #wait_b,r2 mov #psuclear,r0 ; clear psu mov.b r0,@(flmcr1,gbr) wait_12 dt r2 ; wait 5 s bf wait_12 ; mov.l #wdt_tcsr,r0 ; disable wdt mov.w #h'a55f,r1 mov.w r1,@r0 ; no_adwrt2 .equ $ cmp/pl r5 ; if m = 0, end of programming bf program_ok add #1,r14 mov #ng,r13 ; move ng (return value) to r13 mov.l #maxverify,r3 ; if n 1000, programming error cmp/gt r14,r3 bf program_end ; bra program_loop nop ; program_ok .equ $ mov #ok,r13 ; move ok (return value) to r13 program_end .equ $ mov #sweclear,r0 ; clear swe mov.b r0,@(flmcr1,gbr) ; mov.l #wait_f,r2 wait_13 dt r2 ; wait 100 s
345 bf wait_13 ; rts nop ; adatabuff .res.b 128 ; additional programming ram area rdatabuff .res.b 128 ; reprogramming ram area 16.7.3 erase mode flash memory is erased one block at a time using the method shown in figure 16.13, erase/erase- verify flowchart (single-block erasure). to perform data or program erasure, set the 1-bit flash memory area to be erased in erase block register 1 (ebr1) and erase block register 2 (ebr2) at least 1 s after setting the swe bit to 1 in flash memory control register 1 (flmcr1). next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. after this, preparation for erase mode (erase setup) is carried out by setting the esu bit in flmcr1, and after the elapse of 100 s or more, the operating mode is switched to erase mode by setting the e bit in flmcr1. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed 10 ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0 ) is not necessary before starting the erase procedure.
346 16.7.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the erase time, erase mode is exited (the e bit in flmcr1 is cleared, then the esu bit is cleared at least 10 s later), the watchdog timer is cleared after the elapse of 10 s or more, and the operating mode is switched to erase-verify mode by setting the ev bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of 6 s or more. when the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. wait at least 2 s after the dummy write before performing this read operation. if the read data has been erased (all 1 ), a dummy write is performed to the next address, and erase-verify is performed. if the read data has not been erased, set erase mode again, and repeat the erase/erase- verify sequence in the same way. however, ensure that the erase/erase-verify sequence is not repeated more than 100 times. when verification is completed, exit erase-verify mode, and wait for at least 4 s. if erasure has been completed on all the erase blocks, clear the swe bit in flmcr1. if there are any unerased blocks, set 1 bit for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way.
347 end of erase start set swe bit in flmcr1 set esu bit in flmcr1 set e bit in flmcr1 wait 1 s wait 100 s n = 1 set ebr1/ebr2 enable wdt * 3 wait 10 ms wait 10 s wait 10 s wait 6 s set block start address to verify address wait 2 s * 2 wait 4 s * 4 start of erase clear e bit in flmcr1 clear esu bit in flmcr1 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait 4 s clear ev bit in flmcr1 clear swe bit in flmcr1 disable wdt erase halted * 1 verify data = all 1 ? last address of block? erasing of all erase blocks completed? erase failure clear swe bit in flmcr1 wait 100 s wait 100 s n 100? no no no no yes yes yes yes n n + 1 increment address notes: 1. preprogramming (setting erase block data to all 0 ) is not necessary. 2. verify data is read in 32-bit (longword) units. 3. set only one bit in the erase block register (ebr). two or more bits must not be set. 4. erasing is performed in block units. for a multiple-block erase, the individual blocks must be erased sequentially. figure 16.13 erase/erase-verify flowchart (single-block erase)
348 sample single-block erase program: the wait time set values (number of loops) are for the case where f = 20 mhz. for other frequencies, the set value is given by {wait time (s) f (mhz) 4}. registers used r5 (input): memory block table pointer r7 (output): ok (normal) or ng (error) r0 3, 6, 8 9: work registers flmcr1 .equ h?0 ebr1 .equ h?2 ok .equ h? ng .equ h? ewait_x .equ 5 ewait_y .equ 500 ewait_z .equ 50000 ewait_a .equ 50 ewait_b .equ 50 ewait_c .equ 30 ewait_d .equ 10 ewait_e .equ 20 ewait_f .equ 500 wdt_tcsr equ h?fff8610 wdt_6m equ h?57c sweset .equ b?1000000 esuset .equ b?0100000 eset .equ b?0000010 eclear .equ b?1111101 esuclear .equ b?1011111 evset .equ b?0001000 evclear .equ b?1110111 sweclear .equ b?0111111 maxerase .equ 100 ; flasherase .equ $ mov.l #h?fff8500,r0 ldc r0,gbr ; initialize gbr mov.l #1,r2 ;
349 mov,l #ewait_x,r3 mov.l #flmcr1,r0 or.b #sweset,@(r0,gbr) ; set swe ewait_1 subc r2,r3 ; wait 1 s bf ewait_1 ; mov.l #0,r9 ; initialize n (r9) to 0 ; mov.w @(6,r5),r0 mov.w r0,@(ebr1,gbr) ; erase memory block (ebr1/2) setting mov.l @r5,r6 ; erase memory block start address ; r6 setting ; eraseloop .equ $ mov.l #wdt_tcsr,r1 ; enable wdt mov.w #wdt_6m,r3 ; 6.5 ms cycle mov.w r3,@r1 mov.l #ewait_y,r3 mov.l #flmcr1,r0 or.b #esuset,@(r0,gbr) ; set esu ewait_2 subc r2,r3 ; wait 100 s bf ewait_2 ; mov.l #ewait_z,r3 or.b #eset,@(r0,gbr) ; set e ewait_3 subc r2,r3 ; wait 10 ms bf ewait_3 ; mov.l #ewait_a,r3 and.b #eclear,@(r0,gbr) ; clear e ewait_4 subc r2,r3 ; wait 10 s bf ewait_4 ; mov.l #ewait_b,r3 and.b #esuclear,@(r0,gbr) ; clear esu ewait_5 subc r2,r3 ; wait 10 s bf ewait_5
350 ; mov.l #wdt_tcsr,r1 ; disable wdt mov.w #h?55f,r3 mov.w r3,@r1 ; mov.l #ewait_c,r3 or.b #evset,@(r0,gbr) ; set ev ewait_6 subc r2,r3 ; wait 6 s bf ewait_6 ; blockverify_1 .equ $ ; erase-verify mov.l #h?fffffff,r8 mov.l r8,@r6 ; h'ff dummy write mov.l #ewait_d,r3 ewait_7 subc r2,r3 ; wait 2 s bf ewait_7 ; mov.l @r6+,r1 ; read verify data cmp/eq r8,r1 bf blockverify_ng mov.l @(8,r5),r7 cmp/eq r6,r7 ; check for last address of memory block bf blockverify_1 mov.l #ewait_e,r3 and.b #evclear,@(r0,gbr) ; clear ev ewait_8 subc r2,r3 ; wait 4 s bf ewait_8 ; mov.l #ok,r7 ; move ok (return value) to r7 bra flasherase_end ; verify ok nop ; blockverify_ng .equ $ add.l #1,r9 ; if verify ng, assign n+1 to n add.l #-4,r6 ; next verify address mov.l #ewait_e,r3 and.b #evclear,@(r0,gbr) ; clear ev
351 ewait_9 subc r2,r3 ; wait 4 s bf ewait_9 ; mov.l #maxerase,r7 ; if n > 100, erase error cmp/eq r7,r9 bf eraseloop mov.l #ng,r7 ; move ng (return value) to r7 flasherase_end .equ $ mov.l #flmcr1,r0 and.b #sweclear,@(r0,gbr) ; clear swe mov.l #ewait_f,r3 ewait_10 subc r2,r3 ; wait 100 s bf ewait_10 ; rts nop ; ; memory block table memory block start address: ebr value .align 4 flash_blockdata .equ $ eb0 .data.l h?0000000,h?0000100 eb1 .data.l h?0001000,h?0000200 eb2 .data.l h?0002000,h?0000400 eb3 .data.l h?0003000,h?0000800 eb4 .data.l h?0004000,h?0001000 eb5 .data.l h?0005000,h?0002000 eb6 .data.l h?0006000,h?0004000 eb7 .data.l h?0007000,h?0008000 eb8 .data.l h?0008000,h?0000001 eb9 .data.l h?0010000,h?0000002 eb10 .data.l h?0020000,h?0000004 dummy .data.l h?0028000
352 16.7.5 wait time widths in programming/erasing various wait time widths in the program/erase control program provided by the user should be within the specifications shown below. table 16.7 programming/erasing-related wait width specifications flow section item symbol min typ max unit notes programming- related wait time after psu bit setting tspsu 50 50 s wait time after p bit setting (10 s) tsp10 8 10 12 s additional- programming time wait wait time after p bit setting (30 s) tsp30 28 30 32 s programming time wait wait time after p bit setting (200 s) tsp200 198 200 202 s programming time wait wait time after p bit clearing tcp 5 5 s wait time after psu bit clearing tcpsu 5 5 s wait time after pv bit setting tspv 4 4 s wait time after dummy write tspvr 2 2 s wait time after pv bit clearing tcpv 2 2 s erase-related wait time after esu bit setting tsesu 100 100 s wait time after e bit setting tse 10 10 100 ms erase time wait wait time after e bit clearing tce 10 10 s wait time after esu bit clearing tcesu 10 10 s wait time after ev bit setting tsev 6 6 s wait time after dummy write tsevr 2 2 s wait time after ev bit clearing tcev 4 4 s other (common) wait time after swe bit setting tsswe 1 1 s wait time after swe bit clearing tcswe 100 100 s
353 16.8 protection there are two kinds of flash memory program/erase protection, hardware protection and software protection. 16.8.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control register 1 (flmcr1), erase block register 1 (ebr1), and erase block register 2 (ebr2). the flmcr1, ebr1, and ebr2 settings are retained in the error-protected state. (see table 16.8.) table 16.8 hardware protection functions item description program erase fwp pin protection ? when a high level is input to the fwp pin, flmcr1, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. yes yes reset/standby protection ? in a reset (including a wdt overflow reset) and in standby mode, flmcr1, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. ? in a power-on reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes
354 16.8.2 software protection software protection can be implemented by setting the swe bit in flash memory control register 1 (flmcr1), the rams bit in erase block register 1 (ebr1), erase block register 2 (ebr2), and ram emulation register (ramer). when software protection is in effect, setting the p or e bit in flash memory control register 1 (flmcr1) does not cause a transition to program mode or erase mode. (see table 16.9.) table 16.9 software protection functions item description program erase swe bit protection ? clearing the swe bit to 0 in flmcr1 sets the program/erase-protected state for all blocks. (execute in on-chip ram or external memory.) yes yes block specification protection ? erase protection can be set for individual blocks by settings in erase block register 1 (ebr1) and erase block register 2 (ebr2). ? setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. yes emulation protection ? setting the rams bit to 1 in the ram emulation register (ramer) places all blocks in the program/erase-protected state. yes yes
355 16.8.3 error protection in error protection, an error is detected when SH7018 runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the SH7018 malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. fler bit setting conditions are as follows: 1. when flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. immediately after exception processing (excluding a reset) during programming/erasing 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the bus is released during programming/erasing error protection is released only by a power-on reset and in hardware standby mode. figure 16.14 shows the flash memory state transition diagram.
356 rd vf pr er fler = 0 error occurrence res = 0 res = 0 rd vf pr er fler = 0 program mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er fler = 1 error protection mode error protection mode (standby) standby mode flmcr1, ebr1, ebr2 initialization state flmcr1, ebr1, ebr2 initialization state standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd : memory read not possible vf : verify-read not possible pr : programming not possible er : erasing not possible legend res = 0 error occurrence (standby) figure 16.14 flash memory state transitions
357 16.9 flash memory emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramer setting has been made, accesses cannot be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 16.15 shows an example of emulation of real-time flash memory programming. start emulation program end of emulation program tuning ok? yes no set ramer write tuning data to overlap ram execute application program clear ramer write to flash memory emulation block figure 16.15 flowchart for flash memory emulation in ram
358 h'000000 h'004000 h'0073ff h'008000 h'027fff h'007000 h'0043ff h'005000 h'006000 h'0053ff h'0063ff flash memory eb0 to eb3 flash memory eb8 to eb10 this area can be accessed from both the ram area and flash memory area h'fffff800 h'fffffbff on-chip ram eb4 (1 kb) (3 kb) (1 kb) (3 kb) (1 kb) (3 kb) (1 kb) (3 kb) eb7 eb6 eb5 figure 16.16 example of ram overlap operation example in which flash memory block area (eb4) is overlapped 1. set bits rams, ram1, and ram0 in ramer to 1, 0, 0, to overlap part of ram (h'fffff800 to h'fffffbff) onto the area (part of eb4: h'004000 to h'0043ff) for which real-time programming is required. 2. real-time programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb4). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram1 and ram0 (emulation protection). in this state, setting the p or e bit in flash memory control register 1 (flmcr1) will not cause a transition to program mode or erase mode. when actually programming a flash memory area, the rams bit should be cleared to 0.
359 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 16.10 note on flash memory programming/erasing in the on-board programming modes (user mode and user program mode), nmi input should be disabled to give top priority to the program/erase operations (including ram emulation). 16.11 flash memory programmer mode programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. table 16.10 shows the pin settings for programmer mode. for the pin names in programmer mode, see section 1.3.2, pin functions.) table 16.10 programmer mode pin settings pin names settings mode pins: md3, md2, md1, md0 md3 = 1, md2 = 1, md1 = 0, md0 = 1 fwe pin high level input (in auto-program and auto-erase modes) res pin power-on reset circuit xtal, extal pins oscillator circuit note: in programmer mode, the fwp pin has its polarity reversed and functions as the fwe (flash write enable) pin.
360 16.11.1 socket adapter pin correspondence diagram connect the socket adapter to the chip as shown in figure 16.18. this will enable conversion to a 32-pin arrangement. the on-chip rom memory map is shown in figure 16.17, and the socket adapter pin correspondence diagram in figure 16.18. h'00000000 addresses in mcu mode addresses in programmer mode h'00027fff h'00000 h'27fff on-chip rom space 160 kb figure 16.17 on-chip rom memory map
361 hd64f7018 (100 pins) pin no. pin name 2 3 4 5 6 7 9 10 11 12 13 14 16 17 18 19 20 26 42 44 37 53 54 56 58 59 60 61 62 70 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 ce oe we d7 d6 d5 d4 d3 d2 d1 d0 fwe hn28f101p (32 pins) pin no. pin name 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 22 24 31 21 20 19 18 17 15 14 13 1 32 16 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 ce oe we i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 fwe v cc v ss 66 68 51 other than the above 15,30,39,45,52,55,67,69,72,73, 74,79,99,100 1,8,22,25,32,43,57,65,71,76,89, 96 v cc * v ss power-on reset circuit oscillator circuit legend a0 to a17 i/o0 to i/o7 ce oe we fwe : address input : data input/output : chip enable : output enable : write enable : flash write enable note: * includes nmi as well as md0, md1, md2, and md3. socket adapter (conversion to 32- pin arrangement) xtal extal res n.c. (open) figure 16.18 socket adapter pin correspondence diagram
362 16.11.2 programmer mode operation table 16.11 shows how the different operating modes are set when using programmer mode, and table 16.12 lists the commands used in programmer mode. details of each mode are given below. ? memory read mode memory read mode supports byte reads. ? auto-program mode auto-program mode supports programming of 128 bytes at a time. status polling is used to confirm the end of auto-programming. ? auto-erase mode auto-erase mode supports automatic erasing of the entire flash memory. status polling is used to confirm the end of auto-programming. ? status read mode status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the i/o6 signal. in status read mode, error information is output if an error occurs. table 16.11 settings for various operating modes in programmer mode pin names mode fwe ce oe we i/o0 to i/o7 a0 to a17 read h or l l l h data output ain output disable h or l l h h hi-z ain command write h or l l h l data input * ain chip disable h or l h x x hi-z ain notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. * ain indicates that there is also address input in auto-program mode. 3. for command writes in auto-program and auto-erase modes, input a high level to the fwe pin.
363 table 16.12 programmer mode commands number 1st cycle 2nd cycle command name of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 16.11.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. once memory read mode has been entered, consecutive reads can be performed. 4. after powering on, memory read mode is entered. table 16.13 ac characteristics in transition to memory read mode (conditions: v cc = 3.3 v ?0.3 v, v ss = 0 v, t a = 25? ??) item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30 ns we fall time t f 30 ns
364 ce oe ce a17 to a0 oe we i/o7 to i/o0 note: data is latched on the rising edge of we . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 16.19 timing waveforms for memory read after command write table 16.14 ac characteristics in transition from memory read mode to another mode (conditions: v cc = 3.3 v ?0.3 v, v ss = 0 v, t a = 25? ??) item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30 ns we fall time t f 30 ns
365 ce oe ce a17 to a0 oe we i/o7 to i/o0 note: do not enable we and oe at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh another mode command write memory read mode figure 16.20 timing waveforms in transition from memory read mode to another mode table 16.15 ac characteristics in memory read mode (conditions: v cc = 3.3 v ?0.3 v, v ss = 0 v, t a = 25? ??) item symbol min max unit notes access time t acc 20 s ce output delay time t ce 150 ns oe output delay time t oe 150 ns output disable delay time t df 100 ns data output hold time t oh 5 ns ce a17 to a0 oe we i/o7 to i/o0 v il v il v ih t acc t acc t oh t oh address stable address stable figure 16.21 ce and oe enable state read timing waveforms
366 ce a17 to a0 oe we i/o7 to i/o0 v ih t acc t ce t oe t oe t ce t acc t oh t df t df t oh address stable address stable figure 16.22 ce and oe clock system read timing waveforms 16.11.4 auto-program mode 1. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. 2. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 16.23). do not perform transfer after the third cycle. 5. do not perform a command write during a programming operation. 6. perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. 7. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end identification pin). 8. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe .
367 table 16.16 ac characteristics in auto-program mode (conditions: v cc = 3.3 v ?0.3 v, v ss = 0 v, t a = 25? ??) item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t wsts 1 ms status polling access time t spa 150 ns address setup time t as 0 ns address hold time t ah 60 ns memory write time t write 1 3000 ms write setup time t pns 100 ns write end setup time t pnh 100 ns we rise time t r 30 ns we fall time t f 30 ns ce a17 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t pns t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc t pnh address stable h'40 h'00 data transfer 1 to 128byte write operation complete verify signal write normal complete verify signal figure 16.23 auto-program mode timing waveforms
368 16.11.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end identification pin). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . table 16.17 ac characteristics in auto-erase mode (conditions: v cc = 3.3 v ?0.3 v, v ss = 0 v, t a = 25? ??) item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t ests 1 ms status polling access time t spa 150 ns memory erase time t erase 100 40000 ms erase setup time t ens 100 ns erase end setup time t enh 100 ns we rise time t r 30 ns we fall time t f 30 ns
369 ce a17 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t ens t wep t ds t dh t f t r t ests t erase t spa t ces t ceh t nxtc t nxtc t enh h'20 h'20 h'00 erase complete verify signal erase normal complete verify signal figure 16.24 auto-erase mode timing waveforms
370 16.11.6 status read mode 1. status read mode is provided to specify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than a status read mode command write is executed. table 16.18 ac characteristics in status read mode (conditions: v cc = 3.3 v ?0.3 v, v ss = 0 v, t a = 25? ??) item symbol min max unit notes read time after command write t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns oe output delay time t oe 150 ns disable delay time t df 100 ns ce output delay time t ce 150 ns we rise time t r 30 ns we fall time t f 30 ns ce a17 to a0 oe we i/o7 to i/o0 t wep t f t r t oe t df t ds t ds t dh t dh t ces t ceh t ce t ceh t nxtc t nxtc t nxtc t ces h'71 t wep t f t r h'71 note: i/o2 and i/o3 are undefined. figure 16.25 status read mode timing waveforms
371 table 16.19 status read mode return commands pin name i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 attribute normal end identification command error program- ming error erase error program- ming or erase count exceeded effective address error initial value 00000000 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 program- ming error: 1 otherwise: 0 erasing error: 1 otherwise: 0 count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: i/o2 and i/o3 are undefined at present. 16.11.7 status polling 1. i/o7 status polling is a flag that indicates the operating status in auto-program/auto-erase mode. 2. i/o6 status polling is a flag that indicates a normal or abnormal end in auto-program/auto-erase mode. table 16.20 status polling output truth table pin name during internal operation abnormal end normal end i/o7 0101 i/o6 0011 i/o0 to i/o5 0000 16.11.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 16.21 stipulated transition times to command wait state item symbol min max unit standby release (oscillation stabilization time) t osc1 30 ms programmer mode setup time t bmv 10 ms v cc hold time t dwn 0 ms
372 t osc1 t bmv t dwn v cc res fwe memory read mode command wait state automatic write mode automatic erase mode command wait state normal/abnormal complete verify note : for the level of fwe input pin, set v il when using other than the automatic write mode and automatic erase mode. figure 16.26 oscillation stabilization time, boot program transfer time, and power-down sequence 16.11.9 notes on memory programming 1. when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. 2. when performing programming using prom mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by hitachi. for other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming should be performed once only on the same address block. additional programming cannot be performed on previously programmed address blocks.
373 section 17 ram 17.1 overview the SH7018 has 4 kbytes of on-chip ram. the on-chip ram is connected to the cpu by a 32-bit data bus (figure 17.1). the cpu can access data in the on-chip ram in 8, 16, or 32 bit widths. on-chip ram data can always be accessed in one state, making the ram ideal for use as a program area, stack area, or data area, which require high-speed access. the contents of the on- chip ram are held in sleep mode. memory area addresses h'ffffe000 to h'ffffffff are allocated to the on-chip ram. h'fffff000 h'fffff004 h'fffff001 h'fffff005 h'fffff002 h'fffff006 h'fffff003 h'fffff007 h'fffffffc h'fffffffd h'fffffffe h'ffffffff on-chip ram internal data bus (32 bits) figure 17.1 block diagram of ram
374
375 section 18 power-down state 18.1 overview in the power-down state, the cpu functions are halted. this enables a great reduction in power consumption. 18.1.1 power-down states the power-down state is effected by the following two modes: ? sleep mode ? standby mode table 18.1 describes the transition conditions for entering the modes from the program execution state as well as the cpu and peripheral function status in each mode and the procedures for canceling each mode.
376 table 18.1 power-down state conditions state mode entering procedure clock cpu on-chip peripheral modules cpu registers ram i/o ports canceling procedure sleep execute sleep instruction with sby bit set to 0 in sbycr run halt run held held held ? interrupt ? dmac address error ? power-on reset stand- by execute sleep instruction with sby bit set to 1 in sbycr halt halt halt * 1 held held held or high impe- dance * 2 ? nmi interrupt ? power-on reset sbycr: standby control register. sby: standby bit notes: 1. some bits within on-chip peripheral module registers are initialized by the standby mode; some are not. refer to table 18.3, register states in the standby mode, in section 18.4.1, transition to standby mode. also refer to the register descriptions for each peripheral module. 2. the status of the i/o port in standby mode is set by the port high impedance bit (hiz) of the sbycr. refer to section 18.2, standby control register (sbycr). for pin status other than for the i/o port, refer to appendix b, pin status. 18.1.2 related register table 18.2 shows the register used for power-down state control. table 18.2 related register name abbreviation r/w initial value address access size standby control register sbycr r/w h'1f h'ffff8614 8, 16, 32
377 18.2 standby control register (sbycr) the standby control register (sbycr) is a read/write 8-bit register that sets the transition to standby mode, and the port status in standby mode. the sbycr is initialized to h'1f when reset. bit: 7 6 5 4 3 2 1 0 sby hiz initial value: 0 0 0 1 1 1 1 1 r/w: r/w r/w r r r r r r ? bit 7?tandby (sby): specifies transition to the standby mode. the sby bit cannot be set to 1 while the watchdog timer is running (when the timer enable bit (tme) of the wdt timer control/status register (tcsr) is set to 1). to enter the standby mode, always halt the wdt by 0 clearing the tme bit, then set the sby bit. bit 7: sby description 0 executing sleep instruction puts the lsi into sleep mode (initial value) 1 executing sleep instruction puts the lsi into standby mode ? bit 6?ort high impedance (hiz): in the standby mode, this bit selects whether to set the i/o port pin to high impedance or hold the pin status. the hiz bit cannot be set to 1 when the tme bit of the wdt timer control/status register (tcsr) is set to 1. when making the i/o port pin status high impedance, always clear the tme bit to 0 before setting the hiz bit. bit 6: hiz description 0 holds pin status while in standby mode (initial value) 1 keeps pin at high impedance while in standby mode ? bits 5 to 0?eserved: bit 5 is always reads as 0. the write value should always be 0. bits 4 to 0 are always read as 1. the write value should always be 0. 18.3 sleep mode 18.3.1 transition to sleep mode executing the sleep instruction when the sby bit of sbycr is 0 causes a transition from the program execution state to the sleep mode. although the cpu halts immediately after executing the sleep instruction, the contents of its internal registers remain unchanged. the on-chip peripheral modules continue to run during the sleep mode.
378 18.3.2 canceling sleep mode sleep mode is canceled by an interrupt, dmac address error, or power-on reset. cancellation by an interrupt: when an interrupt occurs, the sleep mode is canceled and interrupt exception processing is executed. the sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the cpu? status register (sr) or if an interrupt by an on-chip peripheral module is disabled at the peripheral module. cancellation by a dmac address error: if a dmac address error occurs, the sleep mode is canceled and dmac address error exception processing is executed. cancellation by a power-on reset: a power-on reset resulting from setting the res pin to low level cancels the sleep mode. 18.4 standby mode 18.4.1 transition to standby mode to enter the standby mode, set the sby bit to 1 in sbycr, then execute the sleep instruction. the lsi moves from the program execution state to the standby mode. in the standby mode, power consumption is greatly reduced by halting not only the cpu, but the clock and on-chip peripheral modules as well. cpu register contents and on-chip ram data are held as long as the prescribed voltages are applied. the register contents of some on-chip peripheral modules are initialized, but some are not (table 18.3). the i/o port status can be selected as held or high impedance by the port high impedance bit (hiz) of the sbycr. for pin status other than for the i/o port, refer to appendix b, pin status.
379 table 18.3 register states in the standby mode module registers initialized registers that retain data registers with undefined contents interrupt controller (intc) all registers cache memory (cac) all registers bus state controller (bsc) all registers direct memory access controller (dmac) ? dma channel control registers 0 and 1 (chcr0, chcr1) ? dma operation register (dmaor) ? dma source address registers 0 and 1 (sar0, sar1) ? dma destination address registers 0 and 1 (dar0, dar1) ? dma transfer count registers 0 and 1 (dmatcr0, dmatcr1) multifunction timer pulse unit (mtu) mtu associated registers watchdog timer (wdt) ? bits 7 to 5 (ovf, wt/ it , tme) of the timer control status register (tcsr) ? reset control/status register (rstcsr) ? bits 2 to 0 (cks2 to cks0) of the tcsr ? timer counter (tcnt) serial communication interface (sci) ? receive data register (rdr) ? transmit data register (tdr) ? serial mode register (smr) ? serial control register (scr) ? serial status register (ssr) ? bit rate register (bbr) a/d converter (a/d) all registers compare match timer (cmt) all registers
380 table 18.3 register states in the standby mode (cont) module registers initialized registers that retain data registers with undefined contents pin function controller (pfc) all registers i/o port (i/o) all registers power-down state related standby control register (sbycr) 18.4.2 canceling the standby mode the standby mode is canceled by an nmi interrupt or a power-on reset. cancellation by an nmi: clock oscillation starts when a rising edge or falling edge (selected by the nmi edge select bit (nmie) of the interrupt control register (icr) of the intc) is detected in the nmi signal. this clock is supplied only to the watchdog timer (wdt). a wdt overflow occurs if the time established by the clock select bits (cks2 to cks0) in the tcsr of the wdt elapses before transition to the standby mode. the occurrence of this overflow is used to indicate that the clock has stabilized, so the clock is supplied to the entire chip, the standby mode is canceled, and nmi exception processing begins. when canceling standby mode with nmi interrupts, set the cks2 to cks0 bits so that the wdt overflow period is longer than the oscillation stabilization time. when canceling standby mode with an nmi pin set for falling edge, be sure that the nmi pin level upon entering standby (when the clock is halted) is high level, and that the nmi pin level upon returning from standby (when the clock starts after oscillation stabilization) is low level. when canceling standby mode with an nmi pin set for rising edge, be sure that the nmi pin level upon entering standby (when the clock is halted) is low level, and that the nmi pin level upon returning from standby (when the clock starts after oscillation stabilization) is high level. cancellation by a power-on reset: a power-on reset caused by setting the res pin to low level cancels the standby mode.
381 18.4.3 standby mode application example this example describes a transition to standby mode on the falling edge of an nmi signal, and a cancellation on the rising edge of the nmi signal. the timing is shown in figure 18.1. when the nmi pin is changed from high to low level while the nmi edge select bit (nmie) of the icr is set to 0 (falling edge detection), the nmi interrupt is accepted. when the nmie bit is set to 1 (rising edge detection) by an nmi exception service routine, the standby bit (sby) of the sbycr is set to 1, and a sleep instruction is executed, standby mode is entered. thereafter, standby mode is canceled when the nmi pin is changed from low to high level. after the nmi pin is changed to high level, this level should be held until nmi exception handling begins. oscillator ck nmi nmie sby nmi exception processing exception service routine sby = 1 sleep instruction standby mode oscillation start time wdt time set nmi exception processing oscillation settling time figure 18.1 standby mode nmi timing (application example)
382
383 section 19 electrical characteristics 19.1 absolute maximum ratings the absolute maximum ratings are listed in table 19.1. table 19.1 absolute maximum ratings item symbol value unit power supply voltage v cc ?.3 to +4.3 v input voltage (except a/d ports) v in ?.3 to v cc +0.3 v input voltage (a/d ports) v in ?.3 to av cc +0.3 v analog power supply voltage av cc ?.3 to +4.3 v analog input voltage v an ?.3 to av cc +0.3 v operating temperature t opr ?0 to +75 ? write/erase temperature t we 0 to +70 ? storage temperature t stg ?5 to +125 ? note: permanent damage to the chip may result if the absolute maximum ratings are exceeded.
384 19.2 dc characteristics the dc characteristics are listed in table 19.2. table 19.2 dc characteristics conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min typ max unit test conditions input high-level res , nmi v ih pv cc ?0.7 pv cc + 0.3 v voltage fwp v cc ?0.3 v cc + 0.3 v extal v cc 0.9 v cc + 0.3 v a/d ports v cc 0.75 av cc + 0.3 v pd0 to pd7, pa3, pa4, pb8 2.2 pv cc + 0.3 v other input pins (except for schmitt trigger) v cc 0.75 v cc + 0.3 v input low-level res , nmi v il ?.3 0.5 v voltage fwp ?.3 v cc 0.1 v pd0 to pd7, pa3, pa4, pb8 ?.3 0.8 v other input pins ?.3 v cc 0.2 v schmitt-trigger input voltage pa2, pa5, pe0, pe2 v t + v t v t + ? t 4.0 0.4 1.0 v v v pa6 to pa9, pe4 to pe14 v t + ? t 0.2 v
385 table 19.2 dc characteristics (cont) conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min typ max unit test conditions input leakage current res , nmi, fwp, pa2, pa5 to pa9, pe0, pe2, pe4 to pe14 |i in | 1.0 ? v in = 0.5 to v cc ?.5v a/d ports 1.0 ? v in = 0.5 to av cc ?.5v other input pins 1.0 ? v in = 0.5 to v cc ?.5v three-state leakage current (off state) a21 to a0, d7 to d0, cs3 to cs0 , wrl , rd , ports a and e |i tsi | 1.0 ? v in = 0.5 to v cc ?.5v output high- level voltage pe0, pe2, pd0 to pd7, pa2 to pa5, pb8 v oh pv cc 0.7 v i oh = ?00 ? pv cc 1.0 v i oh = ?ma other output pins v cc ?0.7 v i oh = ?00 ? v cc ?1.0 v i oh = ?ma output low- level voltage pe0, pe2, pd0 to pd7, pa2 to pa5, pb8 v ol 0.4 v i ol = 1.6ma other output pins 0.6 v i ol = 1.6ma
386 table 19.2 dc characteristics (cont) conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min typ max unit test conditions input capacitance res nmi all other input pins c in 80 50 20 pf pf pf v in = 0 v f = 1 mhz t a = 25? current normal operation i cc 80 110 ma f = 20 mhz consumption sleep mode 70 95 ma f = 20 mhz standby mode 5 50 at a 50? 300 a 50? < t a analog power supply current ai cc 5 10 ma f = 20 mhz notes: 1. if the a/d converter is not used, do not leave the av cc and av ss pins open. connect the av cc pin to v cc and the av ss pin to v ss . 2. current consumption values are for conditions of v ih min = v cc ?.5 v and v il min = 0.5 v with all output pins unloaded. table 19.3 permissible output current values conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min typ max unit output low-level permissible current (per pin) i ol 2.0 ma output low-level permissible current (total) i ol 80ma output high-level permissible current (per pin) ? oh 2.0 ma output high-level permissible current (total) (? oh ) 25ma note: to ensure chip reliability, do not exceed the output current values in table 19.3.
387 19.3 ac characteristics 19.3.1 clock timing the clock timing is shown in table 19.4. table 19.4 clock timing conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min max unit figure operating frequency f op 4 20 mhz figure 19.1 clock cycle time t cyc 50 250 ns clock low-level pulse width t cl 15 ns clock high-level pulse width t ch 15 ns clock rise time t cr ? ns clock fall time t cf ? ns extal clock input frequency f ex 4 20 mhz figure 19.2 extal clock input cycle time t excyc 50 250 ns extal clock input low-level pulse width t exl 17.5 ns extal clock input high-level pulse width t exh 17.5 ns extal clock input rise time t exr ? ns extal clock input fall time t exf ? ns reset oscillation settling time t osc1 10 ms figure 19.3 standby recovery oscillation settling time t osc2 10 ms t cl t cyc t ch ck 1/2 v cc t cf t cr 1/2 v cc figure 19.1 system clock timing
388 t excyc t exl t exh v ih v ih 1/2v cc v il v il 1/2v cc t exf t exr extal v ih figure 19.2 extal clock input timing ck v cc min t osc1 v cc t osc2 res figure 19.3 oscillation settling time
389 19.3.2 control signal timing table 19.5 control signal timing conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min max unit figure res rise and fall t resr , t resf 200 ns figure 19.4 res pulse width t resw 40 t cyc nmi rise and fall t nmir , t nmif 200 ns res setup time * t ress 35 ns figure 19.4, nmi setup time * t nmis 35 ns figure 19.5 irq7 , irq6 , and irq3 to irq0 setup time * (edge detection) t irqes 35 ns irq7 , irq6 , and irq3 to irq0 setup time * (level detection) t irqls 35 ns nmi hold time t nmih 35 ns figure 19.5 irq7 , irq6 , and irq3 to irq0 hold time t irqeh 35 ns note: * the res , nmi, irq7 , irq6 , and irq3 to irq0 signals are input asynchronously. if the setup time indicated is maintained, the clock rise (in the case of res ) or fall (in the case of nmi, irq7 , irq6 , and irq3 to irq0 ) will be recognized as a change in level. if the setup time indicated is not maintained, the change may not be recognized until the next clock rise or fall. ck res t resf t resw t resr t ress t ress v ih v ih v il v il figure 19.4 reset input timing
390 t nmih t nmis v ih v il v il t irqeh t irqes v ih v il t irqls ck nmi irq edge irq level figure 19.5 interrupt signal input timing
391 19.3.3 bus timing table 19.6 bus timing conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min max unit figure address delay time t ad 3 *3 25 ns figure 19.6 to figure 19.8 cs delay time 1 t csd1 3 *3 21 ns figure 19.6 to figure 19.8 cs delay time 2 t csd2 3 *3 21 ns figure 19.6 to figure 19.8 read strobe delay time 1 t rsd1 3 *3 18 ns figure 19.6 to figure 19.8 read strobe delay time 2 t rsd2 3 *3 18 ns figure 19.6 to figure 19.8 read data setup time t rds * 4 20 ns figure 19.6 to figure 19.8 read data hold time t rdh 0 ns figure 19.6 to figure 19.8 write strobe delay time 1 t wsd1 3 *3 18 ns figure 19.6 to figure 19.8 write strobe delay time 2 t wsd2 3 *3 18 ns figure 19.6 to figure 19.8 write data delay time t wdd 35 ns figure 19.6 to figure 19.8 write data hold time t wdh 020 *2 ns figure 19.6 to figure 19.8 wait setup time t wts 20 ns figure 19.6 to figure 19.8 wait hold time t wth 0 ns figure 19.6 to figure 19.8
392 table 19.6 bus timing (cont) conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min max unit figure read data access time t acc * 1 t cyc (n * 5 + 2) 50 ns figure 19.6 to figure 19.8 access time from read strobe t oe * 1 t cyc (n * 5 + 1.5) 50 ns figure 19.6 to figure 19.8 write address setup time t as 0 ns figure 19.6 to figure 19.8 write address hold time t wr 0 ns figure 19.6 to figure 19.8 write data hold time t wrh 0 ns figure 19.6 to figure 19.8 notes: 1. the t rds specification needs not be met as long as the access time specification is met. 2. t wdh (max) is a reference value. 3. the minimum (min) values for delay times are reference (typical) values. 4. t rds is a reference value. 5. the n is the wait number.
393 t 1 t 2 ck a21 to a0 csn rd (read) wrl (write) d7 to d0 (read) d15 to d0 (write) note: t rdh : specified from the fastest negate timing of a21 to a0, csn , or rd . t wdh t wdd t wsd1 t wsd2 t acc t rds t rdh t rsd1 t oe t rsd2 t csd2 t csd1 t ad t as t wr t wrh figure 19.6 basic cycle (no wait)
394 ck a21 to a0 csn rd (read) wrl (write) d7 to d0 (read) d7 to d0 (write) t 1 t w t 2 t ad t csd1 t rsd1 t wsd1 t wdd t rsd2 t csd2 t rds t rdh t wsd2 t wdh t oe t acc t as t wr note: t rdh : specified from the fastest negate timing of a21 to a0, csn , or rd . t wrh figure 19.7 basic cycle (software wait)
395 ck a21 to a0 csn rd (read) wrl (write) d7 to d0 (read) d7 to d0 (write) t 1 t w t w0 t w wait t 2 t wts t wth t wts t wth figure 19.8 basic cycle (wait using two software waits + wait signal)
396 19.3.4 multifunction timer pulse unit timing table 19.7 shows the multifunction timer pulse unit timing. table 19.7 multifunction timer pulse unit timing conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min max unit figure output compare output delay time t tocd 100 ns figure 19.9 input capture input setup time t tics 30 ns ck output compare output input capture input t tocd t tics figure 19.9 mtu input/output timing
397 19.3.5 i/o port timing table 19.8 shows the i/o port timing. table 19.8 i/o port timing conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min max unit figure port output data delay time t pwd 100 ns figure 19.10 port input hold time t prh 100 ns port input setup time t prs 100 ns t prs t prh t pwd t 1 t 2 ck port (read) port (write) figure 19.10 i/o port input/output timing
398 19.3.6 serial communication interface timing table 19.9 shows the serial communication interface timing. table 19.9 serial communication interface timing conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?0.5 v, pv cc v cc , av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, f = 20 mhz, t a = ?0 to +75? item symbol min max unit figure input clock cycle t scyc 4 t cyc figure 19.11 input clock cycle (synchronous) t scyc 6 t cyc input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr 1.5 t cyc input clock fall time t sckf 1.5 t cyc transmit data delay time (synchronous) t txd 100 ns figure 19.12 receive data setup time (synchronous) t rxs 100 ns receive data hold time (synchronous) t rxh 100 ns t sckw t sckr t sckf t scyc sck figure 19.11 input clock timing
399 t scyc t txd t rxs t rxh sck txd (transmit data) rxd (receive data) figure 19.12 sci input/output timing (synchronous mode) 19.3.7 a/d converter timing table 19.10 shows the a/d converter timing. table 19.10 a/d converter timing conditions: v cc = 3.0 to 3.6 v, pv cc = 5.0 ?.5 v, pv cc v cc, av cc v cc , f = 20 mhz, av cc = 3.0 to 3.6 v, v ss = av ss = 0v, t a = ?0 to +75 c item symbol min typ max unit figure a/d conversion start cks = 0 t d 10 17 t cyc figure 19.13 delay time cks = 1 6 9 input sampling time cks = 0 t spl 64 cks = 1 32 a/d conversion time cks = 0 t conv 259 266 cks = 1 131 134
400 (1) (2) ck adf t d t spl t conv (1): write cycle of adcsr (2): address of adcsr t d : a/d conversion start delay time t spl : input sampling time t conv : a/d conversion time address write signal input sampling timing figure 19.13 analog conversion timing
401 19.3.8 test conditions for ac characteristics input reference levels: high: 2.2 v, low: 0.8 v output reference levels: high: 2.0 v, low: 0.8 v i ol lsi output pin dut output v ref c l i oh cl is the total value including the capacitance of the testing jig. the settings for the different pins are as follows. 30 pf: ck, cs0 to cs3 50 pf: a21 to a0, d7 to d0, rd , wrl 70 pf: port output pins other than those listed above and peripheral module output pins. i ol , i oh : capacitance values are listed in section 19.2, dc characteristics and table 19.3, permissible output current values. figure 19.14 output load circuit
402 19.4 a/d converter characteristics table 19.11 a/d converter characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, ta = ?0 to +75?, cks = 0 20.0mhz item min typ max unit resolution 10 10 10 bits conversion time 13.4 s analog input capacitance 20 pf permissible signal source impedance 1k ? nonlinearity error 5 * lsb offset error 5 * lsb full-scale error 5 * lsb quantization error 0.5 * lsb absolute accuracy 6 lsb note: * reference values
403 table 19.12 a/d converter characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc v cc , v ss = av ss = 0 v, ta = ?0 to +75?, cks = 1 20mhz item min typ max unit resolution 10 10 10 bits conversion time 6.7 s analog input capacitance 20 pf permissible signal source impedance 1k ? nonlinearity error 5 * lsb offset error 5 * lsb full-scale error 5 * lsb quantization error 0.5 * lsb absolute accuracy 6 lsb note: * reference values
404
405 appendix a on-chip peripheral module registers table a.1 on-chip peripheral module registers address register bit names h'ffffxxxx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 81b0 smr1 c/ a chr pe o/e stop mp cks1 cks0 sci1 81b1 brr1 81b2 scr1 tie rie te re mpie teie cke1 cke0 81b3 tdr1 81b4 ssr1 tdre rdrf orer fer per tend mpb mpbt 81b5 rdr1 8240 tstr cst2 cst1 cst0 all mtu 8241 tsyr sync2 sync1 sync0 8260 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 ch0 8261 tmdr0 bfb bfa md3 md2 md1 md0 8262 tior0h iob2 iob2 iob1 ioa3 ioa2 ioa1 ioa0 8263 tior0l iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 8264 tier0 ttge tciev tgied tgiec tgieb tgiea 8265 tsr0 tcfv tgfd tgfc tgfb tgfa 8266 tcnt0 8267 8268 tgr0a 8269 826a tgr0b 826b 826c tgr0c 826d 826e tgr0d 826f 8280 tcr1 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 ch1 8281 tmdr1 md3md2md1md0 8282 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 8284 tier1 ttge tciev tgieb tgiea 8285 tsr1 tcfv tgfb tgfa 8286 tcnt1 8287 8288 tgr1a 8289
406 table a.1 on-chip peripheral module registers (cont) address register bit names h'ffffxxxx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 828a tgr1b ch1 mtu 828b 82a0 tcr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 ch2 82a1 tmdr2 md3md2md1md0 82a2 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 82a4 tier2 ttge tciev tgieb tgiea 82a5 tsr2 tcfv tgfb tgfa 82a6 tcnt2 82a7 82a8 tgr2a 82a9 82aa tgr2b 82ab 8348 ipra (irq0) (irq0) (irq0) (irq0) (irq1) (irq1) (irq1) (irq1) intc 8349 (irq2) (irq2) (irq2) (irq2) (irq3) (irq3) (irq3) (irq3) 834a iprb 834b (irq6) (irq6) (irq6) (irq6) (irq7) (irq7) (irq7) (irq7) 834c iprc 834d 834e iprd (mtu0) (mtu0) (mtu0) (mtu0) (mtu0) (mtu0) (mtu0) (mtu0) 834f (mtu1) (mtu1) (mtu1) (mtu1) (mtu1) (mtu1) (mtu1) (mtu1) 8350 ipre (mtu2) (mtu2) (mtu2) (mtu2) (mtu2) (mtu2) (mtu2) (mtu2) 8351 8352 iprf 8353 (sci) (sci) (sci) (sci) 8354 iprg (a/d) (a/d) (a/d) (a/d) 8355 (cmt0) (cmt0) (cmt0) (cmt0) (cmt1) (cmt1) (cmt1) (cmt1) 8356 iprh (wdt) (wdt) (tim2) (tim2) 8357 8358 icr nmil nmie 8359 irq0s irq1s irq2s irq3s irq6s irq7s 835a isr 835b irq0f irq1f irq2f irq3f irq6f irq7f 8382 padrl pa15dr pa14dr pa12dr pa11dr pa10dr pa9dr pa8dr i/o port a 8383 pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr
407 table a.1 on-chip peripheral module registers (cont) address register bit names h'ffffxxxx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 8386 paiorl pa15ior pa14ior pa12ior pa11ior pa10ior pa9ior pa8ior pfc port a 8387 pa7ior pa6ior pa5ior pa4ior pa3ior pa2ior pa1ior pa0ior 838c pacrl1 pa15md pa14md pa12md 838d pa11md pa10md pa9md1 pa9md0 pa8md1 pa8md0 838e pacrl2 pa7md1 pa7md0 pa6md1 pa6md0 pa5md pa4md 838f pa3md pa2md1 pa2md0 8390 pbdr pb9dr pb8dr i/o port b 8391 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr 8394 pbior pb9ior pb8ior pfc 8395 pb7ior pb6ior pb5ior pb4ior pb3ior pb2ior pb1ior pb0ior 8398 pbcr1 8399 pb9md1 pb9md0 pb8md1 pb8md0 839a pbcr2 pb7md1 pb7md0 pb6md1 pb6md0 839b pb3md pb1md pb0md 8392 pcdr pc15dr pc14dr pc13dr pc12dr pc11dr pc10dr pc9dr pc8dr i/o port c 8393 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr 8396 pcior pc15ior pc14ior pc13ior pc12ior pc11ior pc10ior pc9ior pc8ior pfc 8397 pc7ior pc6ior pc5ior pc4ior pc3ior pc2ior pc1ior pc0ior 839c pccr pc15md pc14md pc13md pc12md pc11md pc10md pc9md pc8md 839d pc7md pc6md pc5md pc4md pc3md pc2md pc1md pc0md 83a2 pddrl i/o port d 83a3 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr 83a6 pdiorl pd15ior pd14ior pd13ior pd12ior pd11ior pd10ior pd9ior pd8ior tfc 83a7 pd7ior pd6ior pd5ior pd4ior pd3ior pd2ior pd1ior pd0ior 83ac pdcrl 83ad pd7md pd6md pd5md pd4md pd3md pd2md pd1md pd0md 83b0 pedr pe14dr pe13dr pe12dr i/o port e 83b1 pe7dr pe6dr pe5dr pe4dr pe2dr pe0dr 83b3 pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr i/o port f 83b4 peior pe15ior pe14ior pe13ior pe12ior pe11ior pe10or pe9ior pe8ior pfc port e 83b5 pe7ior pe6ior pe5ior pe4ior pe3ior pe2ior pe1ior pe0ior 83ba pecr2 pe7md pe6md pe5md pe4md 83bb pe2md0 pe0md0 83d0 cmstr allcmt 83d1 str1 str0
408 table a.1 on-chip peripheral module registers (cont) address register bit names h'ffffxxxx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 83d2 cmcsr0 ch0cmt 83d3 cmf cmie cks1 cks0 83d4 cmcnt0 83d5 83d6 cmcor0 83d7 83d8 cmcsr1 ch1 83d9 cmf cmie cks1 cks0 83da cmcnt1 83db 83dc cmcor1 83dd 8420 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d 8421 addral ad1 ad0 8422 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 8423 addrbl ad1 ad0 8424 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 8425 addrcl ad1 ad0 8426 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 8427 addrdl ad1 ad0 8428 adcsr adf adie adst scan cks ch2 ch1 ch0 8429 adcr trge 8580 flmcr1 fwe swe esu psu ev pv e p flash 8581 flmcr2 fler 8582 ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 8583 ebr2 eb10 eb9 eb8 8610 tcsr ovf wi/ it tme cks2 cks1 cks0 wdt 8611 tcnt 8612 rstcsr wovf rste 8613 rstcsr wovf rste 8614 sbycr sby hiz power-down state 8620 bcr1 bsc 8621 a3sz a2sz a1sz a0sz 8622 bcr2 iw31 iw30 iw21 iw20 iw11 iw10 iw01 iw00 8623 cw3 cw2 cw1 cw0 sw3 sw2 sw1 sw0
409 table a.1 on-chip peripheral module registers (cont) address register bit names h'ffffxxxx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 8624 wcr1 w31 w30 w21 w20 bsc 8625 w11 w10 w01 w00 8628 ramer 8629 rams ram1 ram0 862c t2csr tim2 862d cmf cmie cks2 cks1 cks0 862e t2cnt 862f 8630 t2cor 8631
410 appendix b pin states b.1 pin states table b.1 pin states after reset and in power-down state pin state pin function after reset power-down state type pin name power-on sleep clock ck o o system control res ii interrupt nmi i i irq0 to irq3 , irq6 , irq7 zi address bus a0 to a21 o o data bus d0 to d7 z i/o bus control wait zi rd hh cs0 to cs3 hh wrh , wrl hh mtu tioc0a, tioc0c z i/o tioc1a, tioc1b tioc2a, tioc2b sci txd z o rxd z i a/d converter an0 to an7 z i i/o ports pa0 to pa15 z k pb0 to pb9 pc0 to pc15 pd0 to pd7 pe0, pe2, pe4 to pe14 legend: i: input, o: output, h: high-level output, l: low-level output, z: high impedance, k: high impedance for input pins and maintain status for output pins
411 b.2 bus-related signals and pin states table b.2 bus-related signals and pin states on-chip peripheral modules normal external space on-chip 16-bit space 16-bit space pin name ram space 8-bit space upper bytes lower bytes word/ longword upper bytes lower bytes word/ longword cs0 to cs3 h h h h h enabled enabled enabled rd rh h hhh l l l wh h hhh hhh wrh rh h hhh hhh wh h hhh l hl wrl rh h hhh hhh wh h hhh hl l a21 to a0 address address address address address address address address d7 to d0zzzzzz data data legend: r: read, w: write, h: high-level output, l: low-level output, z: high impedance, enabled: chip select signal corresponding to area being accessed is low-level, otherwise chip select signal is high-level
412 appendix c product lineup table c.1 SH7018 product lineup product name voltage operating frequency marking code package SH7018 3.3 v 20 mhz hd64f7018x20 tfp-100b
413 appendix d package dimensions figure d.1 shows the tfp-100b package dimensions of the SH7018. hitachi code jedec eiaj weight (reference value) tfp-100b conforms 0.5 g unit: mm *dimension including the plating thickness base material dimension 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max *0.17 0.05 0 8 75 51 125 76 100 26 50 m *0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 figure d.1 package dimensions (tfp-100b)
414
SH7018 hardware manual publication date: 1st edition, july 2000 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 2000. all rights reserved. printed in japan.

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